Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (c) 2018 Microsemi Corporation |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <asm/io.h> |
| 8 | #include <asm/addrspace.h> |
| 9 | #include <asm/types.h> |
| 10 | #include <environment.h> |
| 11 | #include <spi.h> |
| 12 | |
| 13 | DECLARE_GLOBAL_DATA_PTR; |
| 14 | |
Lars Povlsen | e9f1492 | 2018-12-20 09:56:05 +0100 | [diff] [blame^] | 15 | enum { |
| 16 | BOARD_TYPE_PCB120 = 0xAABBCC00, |
| 17 | BOARD_TYPE_PCB123, |
| 18 | }; |
Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 19 | |
| 20 | void external_cs_manage(struct udevice *dev, bool enable) |
| 21 | { |
| 22 | u32 cs = spi_chip_select(dev); |
| 23 | /* IF_SI0_OWNER, select the owner of the SI interface |
| 24 | * Encoding: 0: SI Slave |
Lars Povlsen | e9f1492 | 2018-12-20 09:56:05 +0100 | [diff] [blame^] | 25 | * 1: SI Boot Master |
| 26 | * 2: SI Master Controller |
Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 27 | */ |
| 28 | if (!enable) { |
| 29 | writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE | |
| 30 | ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE); |
| 31 | clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, |
| 32 | ICPU_GENERAL_CTRL_IF_SI_OWNER_M, |
| 33 | ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); |
| 34 | } else { |
| 35 | writel(0, BASE_CFG + ICPU_SW_MODE); |
| 36 | clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, |
| 37 | ICPU_GENERAL_CTRL_IF_SI_OWNER_M, |
| 38 | ICPU_GENERAL_CTRL_IF_SI_OWNER(1)); |
| 39 | } |
| 40 | } |
| 41 | |
| 42 | void board_debug_uart_init(void) |
| 43 | { |
| 44 | /* too early for the pinctrl driver, so configure the UART pins here */ |
Lars Povlsen | e9f1492 | 2018-12-20 09:56:05 +0100 | [diff] [blame^] | 45 | mscc_gpio_set_alternate(6, 1); |
| 46 | mscc_gpio_set_alternate(7, 1); |
Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 47 | } |
| 48 | |
| 49 | int board_early_init_r(void) |
| 50 | { |
| 51 | /* Prepare SPI controller to be used in master mode */ |
| 52 | writel(0, BASE_CFG + ICPU_SW_MODE); |
| 53 | clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, |
| 54 | ICPU_GENERAL_CTRL_IF_SI_OWNER_M, |
| 55 | ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); |
| 56 | |
| 57 | /* Address of boot parameters */ |
| 58 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; |
| 59 | return 0; |
| 60 | } |
Lars Povlsen | e9f1492 | 2018-12-20 09:56:05 +0100 | [diff] [blame^] | 61 | |
| 62 | static void do_board_detect(void) |
| 63 | { |
| 64 | u16 dummy = 0; |
| 65 | |
| 66 | /* Enable MIIM */ |
| 67 | mscc_gpio_set_alternate(14, 1); |
| 68 | mscc_gpio_set_alternate(15, 1); |
| 69 | if (mscc_phy_rd(1, 0, 0, &dummy) == 0) |
| 70 | gd->board_type = BOARD_TYPE_PCB120; |
| 71 | else |
| 72 | gd->board_type = BOARD_TYPE_PCB123; |
| 73 | } |
| 74 | |
| 75 | #if defined(CONFIG_MULTI_DTB_FIT) |
| 76 | int board_fit_config_name_match(const char *name) |
| 77 | { |
| 78 | if (gd->board_type == BOARD_TYPE_PCB120 && |
| 79 | strcmp(name, "ocelot_pcb120") == 0) |
| 80 | return 0; |
| 81 | |
| 82 | if (gd->board_type == BOARD_TYPE_PCB123 && |
| 83 | strcmp(name, "ocelot_pcb123") == 0) |
| 84 | return 0; |
| 85 | |
| 86 | return -1; |
| 87 | } |
| 88 | #endif |
| 89 | |
| 90 | #if defined(CONFIG_DTB_RESELECT) |
| 91 | int embedded_dtb_select(void) |
| 92 | { |
| 93 | do_board_detect(); |
| 94 | fdtdec_setup(); |
| 95 | |
| 96 | return 0; |
| 97 | } |
| 98 | #endif |