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wdenkc0218802003-03-27 12:09:35 +00001/*
Shinya Kuribayashi373b16f2008-03-25 21:30:07 +09002 * Cache-handling routined for MIPS CPUs
wdenkc0218802003-03-27 12:09:35 +00003 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenkc0218802003-03-27 12:09:35 +000025#include <config.h>
26#include <version.h>
Shinya Kuribayashi2f5d4142008-03-25 21:30:06 +090027#include <asm/asm.h>
wdenkc0218802003-03-27 12:09:35 +000028#include <asm/regdef.h>
29#include <asm/mipsregs.h>
30#include <asm/addrspace.h>
31#include <asm/cacheops.h>
32
Shinya Kuribayashi2e0e5272008-03-25 21:30:06 +090033#define RA t8
34
Shinya Kuribayashi373b16f2008-03-25 21:30:07 +090035/*
36 * 16kB is the maximum size of instruction and data caches on MIPS 4K,
37 * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
38 *
39 * Note that the above size is the maximum size of primary cache. U-Boot
40 * doesn't have L2 cache support for now.
41 */
42#define MIPS_MAX_CACHE_SIZE 0x10000
wdenkc0218802003-03-27 12:09:35 +000043
Shinya Kuribayashi2e0e5272008-03-25 21:30:06 +090044#define INDEX_BASE KSEG0
45
46 .macro cache_op op addr
47 .set push
48 .set noreorder
49 .set mips3
50 cache \op, 0(\addr)
51 .set pop
52 .endm
53
wdenkc0218802003-03-27 12:09:35 +000054/*
55 * cacheop macro to automate cache operations
56 * first some helpers...
57 */
58#define _mincache(size, maxsize) \
59 bltu size,maxsize,9f ; \
60 move size,maxsize ; \
619:
62
63#define _align(minaddr, maxaddr, linesize) \
64 .set noat ; \
65 subu AT,linesize,1 ; \
66 not AT ; \
67 and minaddr,AT ; \
68 addu maxaddr,-1 ; \
69 and maxaddr,AT ; \
70 .set at
71
72/* general operations */
73#define doop1(op1) \
74 cache op1,0(a0)
75#define doop2(op1, op2) \
76 cache op1,0(a0) ; \
77 nop ; \
78 cache op2,0(a0)
79
80/* specials for cache initialisation */
81#define doop1lw(op1) \
82 lw zero,0(a0)
83#define doop1lw1(op1) \
84 cache op1,0(a0) ; \
85 lw zero,0(a0) ; \
86 cache op1,0(a0)
87#define doop121(op1,op2) \
88 cache op1,0(a0) ; \
89 nop; \
90 cache op2,0(a0) ; \
91 nop; \
92 cache op1,0(a0)
93
94#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
95 .set noreorder ; \
9610: doop##tag##ops ; \
97 bne minaddr,maxaddr,10b ; \
98 add minaddr,linesize ; \
99 .set reorder
100
101/* finally the cache operation macros */
102#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
103 blez n,11f ; \
104 addu n,kva ; \
105 _align(kva, n, cacheLineSize) ; \
106 _oploopn(kva, n, cacheLineSize, tag, ops) ; \
10711:
108
109#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
110 _mincache(n, cacheSize); \
111 blez n,11f ; \
112 addu n,kva ; \
113 _align(kva, n, cacheLineSize) ; \
114 _oploopn(kva, n, cacheLineSize, tag, ops) ; \
11511:
116
117#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
118 vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
119
120#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
121 icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
122
Shinya Kuribayashi18988402008-03-25 21:30:06 +0900123 .macro f_fill64 dst, offset, val
124 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
125 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
126 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
127 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
128 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
129 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
130 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
131 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
132#if LONGSIZE == 4
133 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
134 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
135 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
136 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
137 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
138 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
139 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
140 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
141#endif
142 .endm
143
Shinya Kuribayashi2e0e5272008-03-25 21:30:06 +0900144/*
145 * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
146 */
147LEAF(mips_init_icache)
148 blez a1, 9f
149 mtc0 zero, CP0_TAGLO
150 /* clear tag to invalidate */
151 PTR_LI t0, INDEX_BASE
152 PTR_ADDU t1, t0, a1
1531: cache_op Index_Store_Tag_I t0
154 PTR_ADDU t0, a2
155 bne t0, t1, 1b
156 /* fill once, so data field parity is correct */
157 PTR_LI t0, INDEX_BASE
1582: cache_op Fill t0
159 PTR_ADDU t0, a2
160 bne t0, t1, 2b
161 /* invalidate again - prudent but not strictly neccessary */
162 PTR_LI t0, INDEX_BASE
1631: cache_op Index_Store_Tag_I t0
164 PTR_ADDU t0, a2
165 bne t0, t1, 1b
1669: jr ra
167 END(mips_init_icache)
168
169/*
170 * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
171 */
172LEAF(mips_init_dcache)
173 blez a1, 9f
174 mtc0 zero, CP0_TAGLO
175 /* clear all tags */
176 PTR_LI t0, INDEX_BASE
177 PTR_ADDU t1, t0, a1
1781: cache_op Index_Store_Tag_D t0
179 PTR_ADDU t0, a2
180 bne t0, t1, 1b
181 /* load from each line (in cached space) */
182 PTR_LI t0, INDEX_BASE
1832: LONG_L zero, 0(t0)
184 PTR_ADDU t0, a2
185 bne t0, t1, 2b
186 /* clear all tags */
187 PTR_LI t0, INDEX_BASE
1881: cache_op Index_Store_Tag_D t0
189 PTR_ADDU t0, a2
190 bne t0, t1, 1b
1919: jr ra
192 END(mips_init_dcache)
193
wdenkc0218802003-03-27 12:09:35 +0000194/*******************************************************************************
195*
196* mips_cache_reset - low level initialisation of the primary caches
197*
198* This routine initialises the primary caches to ensure that they
199* have good parity. It must be called by the ROM before any cached locations
200* are used to prevent the possibility of data with bad parity being written to
201* memory.
202* To initialise the instruction cache it is essential that a source of data
203* with good parity is available. This routine
204* will initialise an area of memory starting at location zero to be used as
205* a source of parity.
206*
207* RETURNS: N/A
208*
209*/
Shinya Kuribayashi2f5d4142008-03-25 21:30:06 +0900210NESTED(mips_cache_reset, 0, ra)
Shinya Kuribayashi2e0e5272008-03-25 21:30:06 +0900211 move RA, ra
wdenkc0218802003-03-27 12:09:35 +0000212 li t2, CFG_ICACHE_SIZE
213 li t3, CFG_DCACHE_SIZE
214 li t4, CFG_CACHELINE_SIZE
215 move t5, t4
216
wdenkc0218802003-03-27 12:09:35 +0000217 li v0, MIPS_MAX_CACHE_SIZE
218
Shinya Kuribayashi18988402008-03-25 21:30:06 +0900219 /*
220 * Now clear that much memory starting from zero.
wdenkc0218802003-03-27 12:09:35 +0000221 */
Shinya Kuribayashi18988402008-03-25 21:30:06 +0900222 PTR_LI a0, KSEG1
223 PTR_ADDU a1, a0, v0
2242: PTR_ADDIU a0, 64
225 f_fill64 a0, -64, zero
226 bne a0, a1, 2b
wdenk8bde7f72003-06-27 21:31:46 +0000227
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900228 /*
229 * The caches are probably in an indeterminate state,
230 * so we force good parity into them by doing an
231 * invalidate, load/fill, invalidate for each line.
232 */
wdenkc0218802003-03-27 12:09:35 +0000233
Shinya Kuribayashi2e0e5272008-03-25 21:30:06 +0900234 /*
235 * Assume bottom of RAM will generate good parity for the cache.
wdenkc0218802003-03-27 12:09:35 +0000236 */
237
Shinya Kuribayashi2e0e5272008-03-25 21:30:06 +0900238 /*
239 * Initialize the I-cache first,
wdenkc0218802003-03-27 12:09:35 +0000240 */
Shinya Kuribayashi2e0e5272008-03-25 21:30:06 +0900241 move a1, t2
242 move a2, t4
243 bal mips_init_icache
wdenkc0218802003-03-27 12:09:35 +0000244
Shinya Kuribayashi2e0e5272008-03-25 21:30:06 +0900245 /*
246 * then initialize D-cache.
wdenkc0218802003-03-27 12:09:35 +0000247 */
Shinya Kuribayashi2e0e5272008-03-25 21:30:06 +0900248 move a1, t3
249 move a2, t5
250 bal mips_init_dcache
wdenkc0218802003-03-27 12:09:35 +0000251
Shinya Kuribayashi2e0e5272008-03-25 21:30:06 +0900252 jr RA
Shinya Kuribayashi2f5d4142008-03-25 21:30:06 +0900253 END(mips_cache_reset)
wdenkc0218802003-03-27 12:09:35 +0000254
255/*******************************************************************************
256*
257* dcache_status - get cache status
258*
259* RETURNS: 0 - cache disabled; 1 - cache enabled
260*
261*/
Shinya Kuribayashi2f5d4142008-03-25 21:30:06 +0900262LEAF(dcache_status)
Shinya Kuribayashid98e3482008-03-25 21:30:07 +0900263 mfc0 t0, CP0_CONFIG
264 li t1, CONF_CM_UNCACHED
265 andi t0, t0, CONF_CM_CMASK
266 move v0, zero
267 beq t0, t1, 2f
268 li v0, 1
2692: jr ra
Shinya Kuribayashi2f5d4142008-03-25 21:30:06 +0900270 END(dcache_status)
wdenkc0218802003-03-27 12:09:35 +0000271
272/*******************************************************************************
273*
274* dcache_disable - disable cache
275*
276* RETURNS: N/A
277*
278*/
Shinya Kuribayashi2f5d4142008-03-25 21:30:06 +0900279LEAF(dcache_disable)
wdenkc0218802003-03-27 12:09:35 +0000280 mfc0 t0, CP0_CONFIG
281 li t1, -8
282 and t0, t0, t1
283 ori t0, t0, CONF_CM_UNCACHED
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900284 mtc0 t0, CP0_CONFIG
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900285 jr ra
Shinya Kuribayashi2f5d4142008-03-25 21:30:06 +0900286 END(dcache_disable)
wdenkc0218802003-03-27 12:09:35 +0000287
Shinya Kuribayashiea638952008-05-03 13:51:28 +0900288/*******************************************************************************
289*
290* dcache_enable - enable cache
291*
292* RETURNS: N/A
293*
294*/
295LEAF(dcache_enable)
296 mfc0 t0, CP0_CONFIG
297 ori t0, CONF_CM_CMASK
298 xori t0, CONF_CM_CMASK
299 ori t0, CONF_CM_CACHABLE_NONCOHERENT
300 mtc0 t0, CP0_CONFIG
301 jr ra
302 END(dcache_enable)
303
Shinya Kuribayashie1390802008-03-25 11:39:29 +0900304#ifdef CFG_INIT_RAM_LOCK_MIPS
wdenkc0218802003-03-27 12:09:35 +0000305/*******************************************************************************
306*
307* mips_cache_lock - lock RAM area pointed to by a0 in cache.
308*
309* RETURNS: N/A
310*
311*/
wdenk5da627a2003-10-09 20:09:04 +0000312#if defined(CONFIG_PURPLE)
wdenk60fbe252003-04-08 23:25:21 +0000313# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
wdenk5da627a2003-10-09 20:09:04 +0000314#else
315# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
wdenk60fbe252003-04-08 23:25:21 +0000316#endif
wdenkc0218802003-03-27 12:09:35 +0000317 .globl mips_cache_lock
318 .ent mips_cache_lock
319mips_cache_lock:
wdenk60fbe252003-04-08 23:25:21 +0000320 li a1, K0BASE - CACHE_LOCK_SIZE
wdenkc0218802003-03-27 12:09:35 +0000321 addu a0, a1
wdenk60fbe252003-04-08 23:25:21 +0000322 li a2, CACHE_LOCK_SIZE
wdenkc0218802003-03-27 12:09:35 +0000323 li a3, CFG_CACHELINE_SIZE
324 move a1, a2
325 icacheop(a0,a1,a2,a3,0x1d)
326
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900327 jr ra
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900328
wdenkc0218802003-03-27 12:09:35 +0000329 .end mips_cache_lock
Shinya Kuribayashie1390802008-03-25 11:39:29 +0900330#endif /* CFG_INIT_RAM_LOCK_MIPS */