blob: 371bcd9e6b4eae4b8aeb4a3a213d6f9b7c01e969 [file] [log] [blame]
Anatolij Gustschina3921ee2010-04-24 19:27:09 +02001/*
2 * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
3 *
4 * (C) Copyright 2009-2010
5 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Anatolij Gustschina3921ee2010-04-24 19:27:09 +02008 */
9
10#include <common.h>
11#include <asm/bitops.h>
12#include <command.h>
13#include <asm/io.h>
14#include <asm/processor.h>
15#include <asm/mpc512x.h>
16#include <fdt_support.h>
17#include <flash.h>
18#ifdef CONFIG_MISC_INIT_R
19#include <i2c.h>
20#endif
21#include <serial.h>
22#include <jffs2/load_kernel.h>
23#include <mtd_node.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
27extern flash_info_t flash_info[];
28ulong flash_get_size (phys_addr_t base, int banknum);
29
Anatolij Gustschina3921ee2010-04-24 19:27:09 +020030sdram_conf_t mddrc_config[] = {
31 {
32 (512 << 20), /* 512 MB RAM configuration */
33 {
34 CONFIG_SYS_MDDRC_SYS_CFG,
35 CONFIG_SYS_MDDRC_TIME_CFG0,
36 CONFIG_SYS_MDDRC_TIME_CFG1,
37 CONFIG_SYS_MDDRC_TIME_CFG2
38 }
39 },
40 {
41 (128 << 20), /* 128 MB RAM configuration */
42 {
43 CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
44 CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
45 CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
46 CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
47 }
48 },
49};
50
Simon Glassf1683aa2017-04-06 12:47:05 -060051int dram_init(void)
Anatolij Gustschina3921ee2010-04-24 19:27:09 +020052{
53 int i;
54 u32 msize = 0;
55 u32 pdm360ng_init_seq[] = {
56 CONFIG_SYS_DDRCMD_NOP,
57 CONFIG_SYS_DDRCMD_NOP,
58 CONFIG_SYS_DDRCMD_NOP,
59 CONFIG_SYS_DDRCMD_NOP,
60 CONFIG_SYS_DDRCMD_NOP,
61 CONFIG_SYS_DDRCMD_NOP,
62 CONFIG_SYS_DDRCMD_NOP,
63 CONFIG_SYS_DDRCMD_NOP,
64 CONFIG_SYS_DDRCMD_NOP,
65 CONFIG_SYS_DDRCMD_NOP,
66 CONFIG_SYS_DDRCMD_PCHG_ALL,
67 CONFIG_SYS_DDRCMD_NOP,
68 CONFIG_SYS_DDRCMD_RFSH,
69 CONFIG_SYS_DDRCMD_NOP,
70 CONFIG_SYS_DDRCMD_RFSH,
71 CONFIG_SYS_DDRCMD_NOP,
72 CONFIG_SYS_MICRON_INIT_DEV_OP,
73 CONFIG_SYS_DDRCMD_NOP,
74 CONFIG_SYS_DDRCMD_EM2,
75 CONFIG_SYS_DDRCMD_NOP,
76 CONFIG_SYS_DDRCMD_PCHG_ALL,
77 CONFIG_SYS_DDRCMD_EM2,
78 CONFIG_SYS_DDRCMD_EM3,
79 CONFIG_SYS_DDRCMD_EN_DLL,
80 CONFIG_SYS_DDRCMD_RES_DLL,
81 CONFIG_SYS_DDRCMD_PCHG_ALL,
82 CONFIG_SYS_DDRCMD_RFSH,
83 CONFIG_SYS_DDRCMD_RFSH,
84 CONFIG_SYS_MICRON_INIT_DEV_OP,
85 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
86 CONFIG_SYS_DDRCMD_OCD_EXIT,
87 CONFIG_SYS_DDRCMD_PCHG_ALL,
88 CONFIG_SYS_DDRCMD_NOP
89 };
90
91 for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
92 msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
93 ARRAY_SIZE(pdm360ng_init_seq));
94 if (msize == mddrc_config[i].size)
95 break;
96 }
97
Simon Glass088454c2017-03-31 08:40:25 -060098 gd->ram_size = msize;
99
100 return 0;
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200101}
102
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200103static int set_lcd_brightness(char *);
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200104
105int misc_init_r(void)
106{
107 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
108
109 /*
110 * Re-configure flash setup using auto-detected info
111 */
112 if (flash_info[1].size > 0) {
113 out_be32(&im->sysconf.lpcs1aw,
114 CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
115 CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
116 flash_info[1].size));
117 sync_law(&im->sysconf.lpcs1aw);
118 /*
119 * Re-check to get correct base address
120 */
121 flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
122 } else {
123 /* Disable Bank 1 */
124 out_be32(&im->sysconf.lpcs1aw, 0x01000100);
125 sync_law(&im->sysconf.lpcs1aw);
126 }
127
128 out_be32(&im->sysconf.lpcs0aw,
129 CSAW_START(gd->bd->bi_flashstart) |
130 CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
131 sync_law(&im->sysconf.lpcs0aw);
132
133 /*
134 * Re-check to get correct base address
135 */
136 flash_get_size (gd->bd->bi_flashstart, 0);
137
138 /*
139 * Re-do flash protection upon new addresses
140 */
141 flash_protect (FLAG_PROTECT_CLEAR,
142 gd->bd->bi_flashstart, 0xffffffff,
143 &flash_info[0]);
144
145 /* Monitor protection ON by default */
146 flash_protect (FLAG_PROTECT_SET,
147 CONFIG_SYS_MONITOR_BASE,
148 CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
149 &flash_info[0]);
150
151 /* Environment protection ON by default */
152 flash_protect (FLAG_PROTECT_SET,
153 CONFIG_ENV_ADDR,
154 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
155 &flash_info[0]);
156
157#ifdef CONFIG_ENV_ADDR_REDUND
158 /* Redundant environment protection ON by default */
159 flash_protect (FLAG_PROTECT_SET,
160 CONFIG_ENV_ADDR_REDUND,
161 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
162 &flash_info[0]);
163#endif
164
165#ifdef CONFIG_FSL_DIU_FB
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200166 set_lcd_brightness(0);
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200167 /* Switch LCD-Backlight and LVDS-Interface on */
168 setbits_be32(&im->gpio.gpdir, 0x01040000);
169 clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
170#endif
171
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200172 return 0;
173}
174
175static iopin_t ioregs_init[] = {
176 /* FUNC1=LPC_CS4 */
177 {
178 offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
179 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
180 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
181 },
182 /* FUNC3=GPIO10 */
183 {
184 offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
185 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
186 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
187 },
188 /* FUNC1=CAN3_TX */
189 {
190 offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
191 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
192 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
193 },
194 /* FUNC3=GPIO14 */
195 {
196 offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
197 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
198 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
199 },
200 /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
201 /* DIU_LD22-DIU_LD23 */
202 {
203 offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
204 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
205 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
206 },
207 /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
208 /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
209 {
210 offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
211 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
212 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
213 },
214 /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
215 /* VIU_DATA0-VIU_DATA2 */
216 {
217 offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
218 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
219 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
220 },
221 /* FUNC2=FEC_TXD_0 */
222 {
223 offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
224 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
225 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
226 },
227 /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
228 /* VIU_DATA3, VIU_DATA4 */
229 {
230 offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
231 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
232 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
233 },
234 /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
235 /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
236 /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
237 {
238 offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
239 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
240 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
241 },
242 /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
243 /* DIU_LD00-DIU_LD21 */
244 {
245 offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
246 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
247 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
248 },
249 /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
250 /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
251 {
252 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
253 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
254 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
255 },
256 /* FUNC2=CAN3_RX */
257 {
258 offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
259 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
260 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
261 },
262 /* Sets lowest slew on 2 CAN_TX Pins*/
263 {
264 offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
265 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
266 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
267 },
268 /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
269 /* CAN4_TX, CAN4_RX */
270 {
271 offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
272 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
273 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
274 },
275 /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
276 /* GPIO8, GPIO9 */
277 {
278 offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
279 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
280 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
281 },
282 /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
283 /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
284 {
285 offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
286 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
287 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
288 },
289 /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
290 /* FEC_RXD_3, FEC_RXD_2 */
291 {
292 offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
293 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
294 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
295 },
296 /* FUNC3=GPIO17 */
297 {
298 offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
299 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
300 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
301 },
302 /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
303 /* GPIO2, GPIO20, GPIO21 */
304 {
305 offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
306 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
307 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
308 },
309 /* FUNC2=VIU_PIX_CLK */
310 {
311 offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
312 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
313 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
314 },
315 /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
316 /* GPIO24, GPIO25 */
317 {
318 offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
319 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
320 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
321 },
322 /* FUNC1=NFC_CE2 */
323 {
324 offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
325 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
326 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
327 },
328 /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
329 /* VIU_DATA5-VIU_DATA9 */
330 {
331 offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
332 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
333 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
334 },
335 /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
336 /* LPC_TSIZ1-LPC_TSIZ2 */
337 {
338 offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
339 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
340 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
341 },
342 /* FUNC1=LPC_TS */
343 {
344 offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
345 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
346 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
347 },
348 /* FUNC3=GPIO16 */
349 {
350 offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
351 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
352 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
353 },
354 /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
355 /* GPIO18-GPIO19, GPT7/GPIO7 */
356 {
357 offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
358 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
359 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
360 },
361 /* FUNC3=GPIO0/GPT0 */
362 {
363 offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
364 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
365 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
366 },
367 /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
368 /* GPIO11, GPIO2, GPIO12, GPIO13 */
369 {
370 offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
371 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
372 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
373 },
374 /* FUNC2=DIU_DE */
375 {
376 offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
377 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
378 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
379 }
380};
381
382int checkboard (void)
383{
384 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
385
386 puts("Board: PDM360NG\n");
387
388 /* initialize function mux & slew rate IO inter alia on IO Pins */
389
390 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
391
392 /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
393 setbits_be32(&im->io_ctrl.io_control_gp,
394 (1 << 0) | /* GP_MUX7->GPIO7 */
395 (1 << 5)); /* GP_MUX2->GPIO2 */
396
397 /* configure GPIO24 (VIU_CE), output/high */
398 setbits_be32(&im->gpio.gpdir, 0x80);
399 setbits_be32(&im->gpio.gpdat, 0x80);
400
401 return 0;
402}
403
Robert P. J. Day7ffe3cd2016-05-19 15:23:12 -0400404#ifdef CONFIG_OF_BOARD_SETUP
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200405#ifdef CONFIG_FDT_FIXUP_PARTITIONS
406struct node_info nodes[] = {
407 { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
408 { "cfi-flash", MTD_DEV_TYPE_NOR, },
409};
410#endif
411
Anatolij Gustschin6213b8f2010-08-17 17:46:02 +0200412#if defined(CONFIG_VIDEO)
413/*
414 * EDID block has been generated using Phoenix EDID Designer 1.3.
415 * This tool creates a text file containing:
416 *
417 * EDID BYTES:
418 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
419 * ------------------------------------------------
420 * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
421 * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
422 * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
423 * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
424 * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
425 * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
426 * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
427 * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
428 *
429 * Then this data has been manually converted to the char
430 * array below.
431 */
432static unsigned char edid_buf[128] = {
433 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
434 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
435 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
436 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
437 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
438 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
439 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
440 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
441 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
442 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
443 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
444 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
445 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
446 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
447 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
448 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
449};
450#endif
451
Simon Glasse895a4b2014-10-23 18:58:47 -0600452int ft_board_setup(void *blob, bd_t *bd)
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200453{
454 u32 val[8];
455 int rc, i = 0;
456
457 ft_cpu_setup(blob, bd);
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200458#ifdef CONFIG_FDT_FIXUP_PARTITIONS
459 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
460#endif
Anatolij Gustschin6213b8f2010-08-17 17:46:02 +0200461#if defined(CONFIG_VIDEO)
462 fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
463#endif
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200464
465 /* Fixup NOR FLASH mapping */
466 val[i++] = 0; /* chip select number */
467 val[i++] = 0; /* always 0 */
468 val[i++] = gd->bd->bi_flashstart;
469 val[i++] = gd->bd->bi_flashsize;
470
471 /* Fixup MRAM mapping */
472 val[i++] = 2; /* chip select number */
473 val[i++] = 0; /* always 0 */
474 val[i++] = CONFIG_SYS_MRAM_BASE;
475 val[i++] = CONFIG_SYS_MRAM_SIZE;
476
477 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
478 val, i * sizeof(u32), 1);
479 if (rc)
480 printf("Unable to update localbus ranges, err=%s\n",
481 fdt_strerror(rc));
482
483 /* Fixup reg property in NOR Flash node */
484 i = 0;
485 val[i++] = 0; /* always 0 */
486 val[i++] = 0; /* start at offset 0 */
487 val[i++] = flash_info[0].size; /* size of Bank 0 */
488
489 /* Second Bank available? */
490 if (flash_info[1].size > 0) {
491 val[i++] = 0; /* always 0 */
492 val[i++] = flash_info[0].size; /* offset of Bank 1 */
493 val[i++] = flash_info[1].size; /* size of Bank 1 */
494 }
495
496 rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
497 val, i * sizeof(u32), 1);
498 if (rc)
499 printf("Unable to update flash reg property, err=%s\n",
500 fdt_strerror(rc));
Simon Glasse895a4b2014-10-23 18:58:47 -0600501
502 return 0;
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200503}
Robert P. J. Day7ffe3cd2016-05-19 15:23:12 -0400504#endif /* CONFIG_OF_BOARD_SETUP */
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200505
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200506/*
507 * If argument is NULL, set the LCD brightness to the
508 * value from "brightness" environment variable. Set
509 * the LCD brightness to the value specified by the
510 * argument otherwise. Default brightness is zero.
511 */
512#define MAX_BRIGHTNESS 99
513static int set_lcd_brightness(char *brightness)
514{
515 struct stdio_dev *cop_port;
516 char *env;
517 char cmd_buf[20];
518 int val = 0;
519 int cs = 0;
520 int len, i;
521
522 if (brightness) {
523 val = simple_strtol(brightness, NULL, 10);
524 } else {
525 env = getenv("brightness");
526 if (env)
527 val = simple_strtol(env, NULL, 10);
528 }
529
530 if (val < 0)
531 val = 0;
532
533 if (val > MAX_BRIGHTNESS)
534 val = MAX_BRIGHTNESS;
535
536 sprintf(cmd_buf, "$SB;%04d;", val);
537
538 len = strlen(cmd_buf);
539 for (i = 1; i <= len; i++)
540 cs += cmd_buf[i];
541
542 cs = (~cs + 1) & 0xff;
543 sprintf(cmd_buf + len, "%02X\n", cs);
544
545 /* IO Coprocessor communication */
546 cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
547 if (!cop_port) {
548 printf("Error: Can't open IO Coprocessor port.\n");
549 return -1;
550 }
551
552 debug("%s: cmd: %s", __func__, cmd_buf);
553 write_port(cop_port, cmd_buf);
554 /*
555 * Wait for transmission and maybe response data
556 * before closing the port.
557 */
558 udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
559 memset(cmd_buf, 0, sizeof(cmd_buf));
560 len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
561 if (len)
562 printf("Error: %s\n", cmd_buf);
563
564 close_port(4);
565
566 return 0;
567}
568
569static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200570 int argc, char * const argv[])
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200571{
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200572 if (argc < 2)
573 return cmd_usage(cmdtp);
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200574
575 return set_lcd_brightness(argv[1]);
576}
577
578U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
579 "set LCD brightness",
580 "<brightness> - set LCD backlight level to <brightness>.\n"
581);