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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ea8fbba73184a40437bdeccd888cf448d5f1105e / . / include / configs / cpu9260.h
blob: 38f34c27a950df89c8a6f7e232d6dcdf776a7437 [file] [log] [blame]
Tom Rix23b80982009-09-27 11:10:09 -0500[diff] [blame]1/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * (C) Copyright 2009
8 * Eric Benard <eric@eukrea.com>
9 *
10 * Configuration settings for the Eukrea CPU9260 board.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
Jens Scharsig425de622010-02-03 22:45:42 +0100[diff] [blame]34#define CONFIG_AT91_LEGACY
35
Tom Rix23b80982009-09-27 11:10:09 -0500[diff] [blame]36#define CONFIG_DISPLAY_CPUINFO 1
37
38#define AT91_MAIN_CLOCK 18432000
39#define CONFIG_SYS_HZ 1000
40
41#define CONFIG_ARM926EJS 1
42
43#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260)
44#define CONFIG_CPU9260 1
45#elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20)
46#define CONFIG_CPU9G20 1
47#endif
48
49#if defined(CONFIG_CPU9G20)
50#define CONFIG_AT91SAM9G20 1
51#elif defined(CONFIG_CPU9260)
52#define CONFIG_AT91SAM9260 1
53#else
54#error "Unknown board"
55#endif
56
57#define CONFIG_ARCH_CPU_INIT
58#undef CONFIG_USE_IRQ
59
60#define CONFIG_CMDLINE_TAG 1
61#define CONFIG_SETUP_MEMORY_TAGS 1
62#define CONFIG_INITRD_TAG 1
63
64/* clocks */
65#if defined(CONFIG_CPU9G20)
66#define MASTER_PLL_DIV 0x01
67#define MASTER_PLL_MUL 0x2B
68#elif defined(CONFIG_CPU9260)
69#define MASTER_PLL_DIV 0x09
70#define MASTER_PLL_MUL 0x61
71#endif
72
73/* CKGR_MOR - enable main osc. */
74#define CONFIG_SYS_MOR_VAL \
75 (AT91_PMC_MOSCEN | \
76 (255 << 8)) /* Main Oscillator Start-up Time */
77#if defined(CONFIG_CPU9G20)
78#define CONFIG_SYS_PLLAR_VAL \
79 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
80 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
81#elif defined(CONFIG_CPU9260)
82#define CONFIG_SYS_PLLAR_VAL \
83 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
84 AT91_PMC_OUT | \
85 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
86#endif
87
88#if defined(CONFIG_CPU9G20)
89#define CONFIG_SYS_MCKR1_VAL \
90 (AT91_PMC_CSS_PLLA | \
91 AT91_PMC_PRES_1 | \
92 AT91SAM9_PMC_MDIV_6 | \
93 AT91_PMC_PDIV_2)
94#define CONFIG_SYS_MCKR2_VAL \
95 CONFIG_SYS_MCKR1_VAL
96#elif defined(CONFIG_CPU9260)
97#define CONFIG_SYS_MCKR1_VAL \
98 (AT91_PMC_CSS_SLOW | \
99 AT91_PMC_PRES_1 | \
100 AT91SAM9_PMC_MDIV_2 | \
101 AT91_PMC_PDIV_1)
102#define CONFIG_SYS_MCKR2_VAL \
103 (AT91_PMC_CSS_PLLA | \
104 AT91_PMC_PRES_1 | \
105 AT91SAM9_PMC_MDIV_2 | \
106 AT91_PMC_PDIV_1)
107#endif
108
109/* define PDC[31:16] as DATA[31:16] */
110#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
111/* no pull-up for D[31:16] */
112#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
113
114/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
115#define CONFIG_SYS_MATRIX_EBICSA_VAL \
116 (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\
117 AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL)
118
119/* SDRAM */
120/* SDRAMC_MR Mode register */
121#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
122/* SDRAMC_TR - Refresh Timer register */
123#define CONFIG_SYS_SDRC_TR_VAL1 0x287
124/* SDRAMC_CR - Configuration register*/
125#if defined(CONFIG_CPU9G20)
126#define CONFIG_SYS_SDRC_CR_VAL_64MB \
127 (AT91_SDRAMC_NC_9 | \
128 AT91_SDRAMC_NR_13 | \
129 AT91_SDRAMC_NB_4 | \
130 AT91_SDRAMC_CAS_2 | \
131 AT91_SDRAMC_DBW_32 | \
132 (2 << 8) | /* Write Recovery Delay */ \
133 (9 << 12) | /* Row Cycle Delay */ \
134 (3 << 16) | /* Row Precharge Delay */ \
135 (3 << 20) | /* Row to Column Delay */ \
136 (6 << 24) | /* Active to Precharge Delay */ \
137 (10 << 28)) /* Exit Self Refresh to Active Delay */
138
139#define CONFIG_SYS_SDRC_CR_VAL_128MB \
140 (AT91_SDRAMC_NC_10 | \
141 AT91_SDRAMC_NR_13 | \
142 AT91_SDRAMC_NB_4 | \
143 AT91_SDRAMC_CAS_2 | \
144 AT91_SDRAMC_DBW_32 | \
145 (2 << 8) | /* Write Recovery Delay */ \
146 (9 << 12) | /* Row Cycle Delay */ \
147 (3 << 16) | /* Row Precharge Delay */ \
148 (3 << 20) | /* Row to Column Delay */ \
149 (6 << 24) | /* Active to Precharge Delay */ \
150 (10 << 28)) /* Exit Self Refresh to Active Delay */
151#elif defined(CONFIG_CPU9260)
152#define CONFIG_SYS_SDRC_CR_VAL_64MB \
153 (AT91_SDRAMC_NC_9 | \
154 AT91_SDRAMC_NR_13 | \
155 AT91_SDRAMC_NB_4 | \
156 AT91_SDRAMC_CAS_2 | \
157 AT91_SDRAMC_DBW_32 | \
158 (2 << 8) | /* Write Recovery Delay */ \
159 (7 << 12) | /* Row Cycle Delay */ \
160 (2 << 16) | /* Row Precharge Delay */ \
161 (2 << 20) | /* Row to Column Delay */ \
162 (5 << 24) | /* Active to Precharge Delay */ \
163 (8 << 28)) /* Exit Self Refresh to Active Delay */
164
165#define CONFIG_SYS_SDRC_CR_VAL_128MB \
166 (AT91_SDRAMC_NC_10 | \
167 AT91_SDRAMC_NR_13 | \
168 AT91_SDRAMC_NB_4 | \
169 AT91_SDRAMC_CAS_2 | \
170 AT91_SDRAMC_DBW_32 | \
171 (2 << 8) | /* Write Recovery Delay */ \
172 (7 << 12) | /* Row Cycle Delay */ \
173 (2 << 16) | /* Row Precharge Delay */ \
174 (2 << 20) | /* Row to Column Delay */ \
175 (5 << 24) | /* Active to Precharge Delay */ \
176 (8 << 28)) /* Exit Self Refresh to Active Delay */
177#endif
178
179/* Memory Device Register -> SDRAM */
180#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
181#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
182#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
183#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
184#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
185#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
186#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
187#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
188#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
189#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
190#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
191#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
192#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
193#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
194#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
195#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
196#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
197#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
198
199/* setup SMC0, CS0 (NOR Flash) - 16-bit */
200#if defined(CONFIG_CPU9G20)
201#define CONFIG_SYS_SMC0_SETUP0_VAL \
202 (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
203 AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
204#define CONFIG_SYS_SMC0_PULSE0_VAL \
205 (AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) | \
206 AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14))
207#define CONFIG_SYS_SMC0_CYCLE0_VAL \
208 (AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14))
209#define CONFIG_SYS_SMC0_MODE0_VAL \
210 (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
211 AT91_SMC_DBW_16 | \
212 AT91_SMC_TDFMODE | \
213 AT91_SMC_TDF_(3))
214#elif defined(CONFIG_CPU9260)
215#define CONFIG_SYS_SMC0_SETUP0_VAL \
216 (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
217 AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
218#define CONFIG_SYS_SMC0_PULSE0_VAL \
219 (AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) | \
220 AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10))
221#define CONFIG_SYS_SMC0_CYCLE0_VAL \
222 (AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10))
223#define CONFIG_SYS_SMC0_MODE0_VAL \
224 (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
225 AT91_SMC_DBW_16 | \
226 AT91_SMC_TDFMODE | \
227 AT91_SMC_TDF_(2))
228#endif
229
230/* user reset enable */
231#define CONFIG_SYS_RSTC_RMR_VAL \
232 (AT91_RSTC_KEY | \
233 AT91_RSTC_PROCRST | \
234 AT91_RSTC_RSTTYP_WAKEUP | \
235 AT91_RSTC_RSTTYP_WATCHDOG)
236
237/* Disable Watchdog */
238#define CONFIG_SYS_WDTC_WDMR_VAL \
239 (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
240 AT91_WDT_WDV | \
241 AT91_WDT_WDDIS | \
242 AT91_WDT_WDD)
243
244/*
245 * Hardware drivers
246 */
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100[diff] [blame^]247#define CONFIG_AT91_GPIO 1
Tom Rix23b80982009-09-27 11:10:09 -0500[diff] [blame]248#define CONFIG_ATMEL_USART 1
249#undef CONFIG_USART0
250#undef CONFIG_USART1
251#undef CONFIG_USART2
252#define CONFIG_USART3 1 /* USART 3 is DBGU */
253
254#define CONFIG_BOOTDELAY 3
255
256/*
257 * BOOTP options
258 */
259#define CONFIG_BOOTP_BOOTFILESIZE 1
260#define CONFIG_BOOTP_BOOTPATH 1
261#define CONFIG_BOOTP_GATEWAY 1
262#define CONFIG_BOOTP_HOSTNAME 1
263
264/*
265 * Command line configuration.
266 */
267#include <config_cmd_default.h>
268#undef CONFIG_CMD_BDI
269#undef CONFIG_CMD_IMI
270#undef CONFIG_CMD_FPGA
271#undef CONFIG_CMD_LOADS
272#undef CONFIG_CMD_IMLS
273
274#define CONFIG_CMD_PING 1
275#define CONFIG_CMD_DHCP 1
276#define CONFIG_CMD_NAND 1
277#define CONFIG_CMD_USB 1
278#define CONFIG_CMD_FAT 1
279
280/* SDRAM */
281#define CONFIG_NR_DRAM_BANKS 1
282#define PHYS_SDRAM 0x20000000
283#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
284#define PHYS_SDRAM_SIZE 0x08000000 /* 128 MB */
285#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
286#else
287#define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */
288#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
289#endif
290
291/* NAND flash */
292#define CONFIG_NAND_ATMEL 1
293#define NAND_MAX_CHIPS 1
294#define CONFIG_SYS_MAX_NAND_DEVICE 1
295#define CONFIG_SYS_NAND_BASE 0x40000000
296#define CONFIG_SYS_NAND_DBW_8 1
297#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
298#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
299#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
300#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Tom Rix23b80982009-09-27 11:10:09 -0500[diff] [blame]301
302/* NOR flash */
303#define CONFIG_SYS_FLASH_CFI 1
304#define CONFIG_FLASH_CFI_DRIVER 1
305#define PHYS_FLASH_1 0x10000000
306#define PHYS_FLASH_2 0x12000000
307#define CONFIG_SYS_FLASH_BANKS_LIST \
308 { PHYS_FLASH_1, PHYS_FLASH_2 }
309#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
310#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
311#define CONFIG_SYS_MAX_FLASH_BANKS 2
312#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
313#define CONFIG_SYS_FLASH_EMPTY_INFO 1
314#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
315#define CONFIG_SYS_FLASH_PROTECTION 1
316#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
317
318/* Ethernet */
319#define CONFIG_MACB 1
320#define CONFIG_RMII 1
321#define CONFIG_RESET_PHY_R 1
322#define CONFIG_NET_MULTI 1
323#define CONFIG_NET_RETRY_COUNT 20
324#define CONFIG_MACB_SEARCH_PHY 1
325
326/* LEDS */
327/* Status LED */
328#define CONFIG_STATUS_LED 1 /* Status LED enabled */
329#define CONFIG_BOARD_SPECIFIC_LED 1
330#define STATUS_LED_RED 0
331#define STATUS_LED_GREEN 1
332#define STATUS_LED_YELLOW 2
333#define STATUS_LED_BLUE 3
334/* Red */
335#define STATUS_LED_BIT STATUS_LED_RED
336#define STATUS_LED_STATE STATUS_LED_OFF
337#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
338/* Green */
339#define STATUS_LED_BIT1 STATUS_LED_GREEN
340#define STATUS_LED_STATE1 STATUS_LED_OFF
341#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
342/* Yellow */
343#define STATUS_LED_BIT2 STATUS_LED_YELLOW
344#define STATUS_LED_STATE2 STATUS_LED_OFF
345#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
346/* Blue */
347#define STATUS_LED_BIT3 STATUS_LED_BLUE
348#define STATUS_LED_STATE3 STATUS_LED_ON
349#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
350/* Optional value */
351#define STATUS_LED_BOOT STATUS_LED_BIT
352
353#define CONFIG_RED_LED AT91_PIN_PC11
354#define CONFIG_GREEN_LED AT91_PIN_PC12
355#define CONFIG_YELLOW_LED AT91_PIN_PC7
356#define CONFIG_BLUE_LED AT91_PIN_PC9
357
358/* USB */
359#define CONFIG_USB_ATMEL 1
360#define CONFIG_USB_OHCI_NEW 1
361#define CONFIG_DOS_PARTITION 1
362#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
363#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
364#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
365#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
366#define CONFIG_USB_STORAGE 1
367
368#define CONFIG_SYS_LOAD_ADDR 0x21000000
369
370#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
371#define CONFIG_SYS_MEMTEST_END 0x21e00000
372
373#undef CONFIG_SYS_USE_NANDFLASH
374#define CONFIG_SYS_USE_FLASH 1
375
376#if defined(CONFIG_SYS_USE_FLASH)
377#define CONFIG_ENV_IS_IN_FLASH 1
378#define CONFIG_ENV_OFFSET 0x40000
379#define CONFIG_ENV_SECT_SIZE 0x20000
380#define CONFIG_ENV_SIZE 0x20000
381#define CONFIG_ENV_OVERWRITE 1
382
383#define CONFIG_BOOTCOMMAND "run flashboot"
384
385#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
386#define MTDPARTS_DEFAULT \
387 "mtdparts=physmap-flash.0:" \
388 "256k(u-boot)ro," \
389 "128k(u-boot-env)ro," \
390 "1792k(kernel)," \
391 "-(rootfs);" \
392 "atmel_nand:-(nand)"
393
394#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
395
396#if defined(CONFIG_CPU9G20)
397#define CONFIG_SYS_BASEDIR "cpu9G20"
398#elif defined(CONFIG_CPU9260)
399#define CONFIG_SYS_BASEDIR "cpu9260"
400#endif
401
402#define CONFIG_EXTRA_ENV_SETTINGS \
403 "mtdids=" MTDIDS_DEFAULT "\0" \
404 "mtdparts=" MTDPARTS_DEFAULT "\0" \
405 "partition=nand0,0\0" \
406 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
407 "ramboot=tftpboot 0x22000000 cpu9260/uImage;" \
408 "run ramargs;bootm 22000000\0" \
409 "flashboot=run ramargs;bootm 0x10060000\0" \
410 "basedir=" CONFIG_SYS_BASEDIR "\0" \
411 "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
412 "off 0x10000000 0x1003ffff;erase 0x10000000 " \
413 "0x1003ffff;cp.b 0x24000000 0x10000000 " \
414 "$(filesize)\0" \
415 "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
416 " 0x10060000 0x1021ffff;erase 0x10060000 " \
417 "0x1021ffff;cp.b 0x24000000 0x10060000 " \
418 "$(filesize)\0" \
419 "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
420 "protect off 0x10220000 0x13ffffff;erase " \
421 "0x10220000 0x13ffffff;cp.b 0x24000000 " \
422 "0x10220000 $(filesize)\0" \
423 ""
424#endif
425
426#define CONFIG_BAUDRATE 115200
427#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
428
429#if defined(CONFIG_CPU9G20)
430#define CONFIG_SYS_PROMPT "CPU9G20=> "
431#elif defined(CONFIG_CPU9260)
432#define CONFIG_SYS_PROMPT "CPU9260=> "
433#endif
434#define CONFIG_SYS_CBSIZE 256
435#define CONFIG_SYS_MAXARGS 16
436#define CONFIG_SYS_PBSIZE \
437 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
438#define CONFIG_SYS_LONGHELP 1
439#define CONFIG_CMDLINE_EDITING 1
440#define CONFIG_SILENT_CONSOLE 1
441#define CONFIG_NETCONSOLE 1
442
443/*
444 * Size of malloc() pool
445 */
446#define CONFIG_SYS_MALLOC_LEN \
447 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
448#define CONFIG_SYS_GBL_DATA_SIZE 128
449
450#define CONFIG_STACKSIZE (32 * 1024)
451
452#if defined(CONFIG_USE_IRQ)
453#error CONFIG_USE_IRQ not supported
454#endif
455
456#endif