blob: 80bed923292654cddc442c3be794f4cbbae5ea16 [file] [log] [blame]
Ilya Yanok0d19f6c2009-02-10 00:22:31 +01001/*
2 * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
3 *
4 * Based on board/freescale/mx31ads/lowlevel_init.S
5 * by Guennadi Liakhovetski.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <asm/arch/mx31-regs.h>
24
25.macro REG reg, val
26 ldr r2, =\reg
27 ldr r3, =\val
28 str r3, [r2]
29.endm
30
31.macro REG8 reg, val
32 ldr r2, =\reg
33 ldr r3, =\val
34 strb r3, [r2]
35.endm
36
37.macro DELAY loops
38 ldr r2, =\loops
391:
40 subs r2, r2, #1
41 nop
42 bcs 1b
43.endm
44
Stefano Babiceab40f82010-03-31 10:27:47 +020045.macro SETUP_RAM cfg, ctl
46 /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
47 REG 0xB8001010, 0x00000004
48 ldr r3, =\cfg
49 ldr r2, =WEIM_ESDCFG0
50 str r3, [r2]
51 REG 0xB8001000, 0x92100000
52 REG 0x80000f00, 0x12344321
53 REG 0xB8001000, 0xa2100000
54 REG 0x80000000, 0x12344321
55 REG 0x80000000, 0x12344321
56 REG 0xB8001000, 0xb2100000
57 REG8 0x80000033, 0xda
58 REG8 0x81000000, 0xff
59 ldr r3, =\ctl
60 ldr r2, =WEIM_ESDCTL0
61 str r3, [r2]
62 REG 0x80000000, 0xDEADBEEF
63 REG 0xB8001010, 0x0000000c
64
65.endm
Ilya Yanok0d19f6c2009-02-10 00:22:31 +010066/* RedBoot: To support 133MHz DDR */
67.macro init_drive_strength
68 /*
69 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
70 * in SW_PAD_CTL registers
71 */
72
73 /* SDCLK */
74 ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
75 ldr r0, [r1, #0x6C]
76 bic r0, r0, #(1 << 12)
77 str r0, [r1, #0x6C]
78
79 /* CAS */
80 ldr r0, [r1, #0x70]
81 bic r0, r0, #(1 << 22)
82 str r0, [r1, #0x70]
83
84 /* RAS */
85 ldr r0, [r1, #0x74]
86 bic r0, r0, #(1 << 2)
87 str r0, [r1, #0x74]
88
89 /* CS2 (CSD0) */
90 ldr r0, [r1, #0x7C]
91 bic r0, r0, #(1 << 22)
92 str r0, [r1, #0x7C]
93
94 /* DQM3 */
95 ldr r0, [r1, #0x84]
96 bic r0, r0, #(1 << 22)
97 str r0, [r1, #0x84]
98
99 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
100 ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
101pad_loop:
102 ldr r0, [r1, #0x88]
103 bic r0, r0, #(1 << 22)
104 bic r0, r0, #(1 << 12)
105 bic r0, r0, #(1 << 2)
106 str r0, [r1, #0x88]
107 add r1, r1, #4
108 subs r2, r2, #0x1
109 bne pad_loop
110.endm /* init_drive_strength */
111
112.globl lowlevel_init
113lowlevel_init:
114
115 init_drive_strength
116
117 /* Image Processing Unit: */
118 /* Too early to switch display on? */
119 /* Switch on Display Interface */
120 REG IPU_CONF, IPU_CONF_DI_EN
121 /* Clock Control Module: */
122 REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
123
124 DELAY 0x40000
125
126 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
127 /* Switch to MCU PLL */
128 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
129
130 /* 399-133-66.5 */
131 ldr r0, =CCM_BASE
132 ldr r1, =0xFF871650
133 /* PDR0 */
134 str r1, [r0, #0x4]
135 ldr r1, MPCTL_PARAM_399
136 /* MPCTL */
137 str r1, [r0, #0x10]
138
139 /* Set UPLL=240MHz, USB=60MHz */
140 ldr r1, =0x49FCFE7F
141 /* PDR1 */
142 str r1, [r0, #0x8]
143 ldr r1, UPCTL_PARAM_240
144 /* UPCTL */
145 str r1, [r0, #0x14]
146 /* default CLKO to 1/8 of the ARM core */
147 mov r1, #0x00000208
148 /* COSR */
149 str r1, [r0, #0x1c]
150
151 /* Default: 1, 4, 12, 1 */
152 REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
153
Stefano Babiceab40f82010-03-31 10:27:47 +0200154check_ddr_module:
155/* Set stackpointer in internal RAM to call get_ram_size */
156 ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
157 stmfd sp!, {r0-r11, ip, lr}
158 mov ip, lr /* save link reg across call */
159
160 ldr r0,=0x08000000
161 SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB
162 ldr r0,=0x80000000
163 ldr r1,=0x10000000
164 bl get_ram_size
165 ldr r1,=0x10000000
166 cmp r0,r1
167 beq restore_regs
168 SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB
169 ldr r0,=0x80000000
170 ldr r1,=0x08000000
171 bl get_ram_size
172 ldr r1,=0x08000000
173 cmp r0,r1
174 beq restore_regs
175
176restore_regs:
177 ldmfd sp!, {r0-r11, ip, lr}
178 mov lr, ip /* restore link reg */
Ilya Yanok0d19f6c2009-02-10 00:22:31 +0100179
180 mov pc, lr
181
Stefano Babiceab40f82010-03-31 10:27:47 +0200182
Ilya Yanok0d19f6c2009-02-10 00:22:31 +0100183MPCTL_PARAM_399:
184 .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
185UPCTL_PARAM_240:
186 .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0))
Stefano Babiceab40f82010-03-31 10:27:47 +0200187
188 .equ ESDCFG0_128MB, \
189 (0 << 21) + /* tXP */ \
190 (1 << 20) + /* tWTR */ \
191 (2 << 18) + /* tRP */ \
192 (1 << 16) + /* tMRD */ \
193 (0 << 15) + /* tWR */ \
194 (5 << 12) + /* tRAS */ \
195 (1 << 10) + /* tRRD */ \
196 (3 << 8) + /* tCAS */ \
197 (2 << 4) + /* tRCD */ \
198 (0x0F << 0) /* tRC */
199
200 .equ ESDCTL0_128MB, \
201 (1 << 31) + /* enable */ \
202 (0 << 28) + /* mode */ \
203 (0 << 27) + /* supervisor protect */ \
204 (2 << 24) + /* 13 rows */ \
205 (2 << 20) + /* 10 cols */ \
206 (2 << 16) + /* 32 bit */ \
207 (3 << 13) + /* 7.81us (64ms/8192) */ \
208 (0 << 10) + /* power down timer */ \
209 (0 << 8) + /* full page */ \
210 (1 << 7) + /* burst length */ \
211 (0 << 0) /* precharge timer */
212
213 .equ ESDCFG0_256MB, \
214 (3 << 21) + /* tXP */ \
215 (0 << 20) + /* tWTR */ \
216 (2 << 18) + /* tRP */ \
217 (1 << 16) + /* tMRD */ \
218 (0 << 15) + /* tWR */ \
219 (5 << 12) + /* tRAS */ \
220 (1 << 10) + /* tRRD */ \
221 (3 << 8) + /* tCAS */ \
222 (2 << 4) + /* tRCD */ \
223 (7 << 0) /* tRC */
224
225 .equ ESDCTL0_256MB, \
226 (1 << 31) + \
227 (0 << 28) + \
228 (0 << 27) + \
229 (3 << 24) + /* 14 rows */ \
230 (2 << 20) + /* 10 cols */ \
231 (2 << 16) + \
232 (4 << 13) + /* 3.91us (64ms/16384) */ \
233 (0 << 10) + \
234 (0 << 8) + \
235 (1 << 7) + \
236 (0 << 0)