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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +08002/*
3 * Copyright (C) 2015 Freescale Semiconductor
Yangbo Lu34f39ce2021-06-03 10:51:19 +08004 * Copyright 2019-2021 NXP
Mingkai Huf3a8e2b2015-10-26 19:47:52 +08005 */
6
7#ifndef __LS1043A_COMMON_H
8#define __LS1043A_COMMON_H
9
Sumit Garg4139b172017-03-30 09:52:38 +053010/* SPL build */
11#ifdef CONFIG_SPL_BUILD
12#define SPL_NO_FMAN
13#define SPL_NO_DSPI
14#define SPL_NO_PCIE
15#define SPL_NO_ENV
16#define SPL_NO_MISC
17#define SPL_NO_USB
18#define SPL_NO_SATA
19#define SPL_NO_QE
20#define SPL_NO_EEPROM
21#endif
22#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
23#define SPL_NO_MMC
24#endif
Yangbo Lu3c7d6472017-09-15 09:51:58 +080025#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
Sumit Garg4139b172017-03-30 09:52:38 +053026#define SPL_NO_IFC
27#endif
28
Bharat Bhushan5344c7b2017-03-22 12:06:27 +053029#include <asm/arch/stream_id_lsch2.h>
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080030#include <asm/arch/config.h>
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080031
32/* Link Definitions */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080033
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080034#define CONFIG_VERY_BIG_RAM
35#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
36#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
37#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shaohui Xiee994ddd2015-11-23 15:23:48 +080038#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080039
Michael Walle3d3fe8b2020-06-01 21:53:26 +020040#define CPU_RELEASE_ADDR secondary_boot_addr
Hou Zhiqiang831c0682015-10-26 19:47:57 +080041
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080042/* Serial Port */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080043#define CONFIG_SYS_NS16550_SERIAL
44#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang904110c2017-01-10 16:44:15 +080045#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080046
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080047/* SD boot SPL */
48#ifdef CONFIG_SD_BOOT
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080049
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080050#define CONFIG_SPL_STACK 0x1001e000
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080051
York Sun23af4842017-09-28 08:42:16 -070052#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
53 CONFIG_SPL_BSS_MAX_SIZE)
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080054#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
York Sun23af4842017-09-28 08:42:16 -070055#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
Ruchika Gupta70f96612017-04-17 18:07:17 +053056
Udit Agarwal5536c3c2019-11-07 16:11:32 +000057#ifdef CONFIG_NXP_ESBC
Ruchika Gupta70f96612017-04-17 18:07:17 +053058#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
59/*
60 * HDR would be appended at end of image and copied to DDR along
61 * with U-Boot image. Here u-boot max. size is 512K. So if binary
62 * size increases then increase this size in case of secure boot as
63 * it uses raw u-boot image instead of fit image.
64 */
65#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
66#else
67#define CONFIG_SYS_MONITOR_LEN 0x100000
Udit Agarwal5536c3c2019-11-07 16:11:32 +000068#endif /* ifdef CONFIG_NXP_ESBC */
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080069#endif
70
Gong Qianyu3ad44722015-10-26 19:47:53 +080071/* NAND SPL */
72#ifdef CONFIG_NAND_BOOT
Gong Qianyu3ad44722015-10-26 19:47:53 +080073#define CONFIG_SPL_STACK 0x1001d000
74#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
75#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
76#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
77#define CONFIG_SPL_BSS_START_ADDR 0x80100000
78#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
Ruchika Gupta762f92a2017-04-17 18:07:18 +053079
Udit Agarwal5536c3c2019-11-07 16:11:32 +000080#ifdef CONFIG_NXP_ESBC
Ruchika Gupta762f92a2017-04-17 18:07:18 +053081#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
Udit Agarwal5536c3c2019-11-07 16:11:32 +000082#endif /* ifdef CONFIG_NXP_ESBC */
Ruchika Gupta762f92a2017-04-17 18:07:18 +053083
84#ifdef CONFIG_U_BOOT_HDR_SIZE
85/*
86 * HDR would be appended at end of image and copied to DDR along
87 * with U-Boot image. Here u-boot max. size is 512K. So if binary
88 * size increases then increase this size in case of secure boot as
89 * it uses raw u-boot image instead of fit image.
90 */
91#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
92#else
93#define CONFIG_SYS_MONITOR_LEN 0x100000
94#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
95
Gong Qianyu3ad44722015-10-26 19:47:53 +080096#endif
97
Biwen Libe7b6d52021-02-05 19:01:56 +080098/* GPIO */
Biwen Libe7b6d52021-02-05 19:01:56 +080099
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800100/* IFC */
Sumit Garg4139b172017-03-30 09:52:38 +0530101#ifndef SPL_NO_IFC
Rajesh Bhagatf71b5f12018-11-05 18:02:44 +0000102#if defined(CONFIG_TFABOOT) || \
103 (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800104/*
105 * CONFIG_SYS_FLASH_BASE has the final address (core view)
106 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
107 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
108 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
109 */
110#define CONFIG_SYS_FLASH_BASE 0x60000000
111#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
112#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
113
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900114#ifdef CONFIG_MTD_NOR_FLASH
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800115#define CONFIG_SYS_FLASH_QUIET_TEST
116#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
117#endif
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800118#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530119#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800120
121/* I2C */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800122
123/* PCIe */
Sumit Garg4139b172017-03-30 09:52:38 +0530124#ifndef SPL_NO_PCIE
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800125#define CONFIG_PCIE1 /* PCIE controller 1 */
126#define CONFIG_PCIE2 /* PCIE controller 2 */
127#define CONFIG_PCIE3 /* PCIE controller 3 */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800128
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800129#ifdef CONFIG_PCI
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800130#define CONFIG_PCI_SCAN_SHOW
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800131#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530132#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800133
Gong Qianyue0579a52016-01-25 15:16:05 +0800134/* DSPI */
Gong Qianyue0579a52016-01-25 15:16:05 +0800135
Shaohui Xiee8297342015-10-26 19:47:54 +0800136/* FMan ucode */
Sumit Garg4139b172017-03-30 09:52:38 +0530137#ifndef SPL_NO_FMAN
Shaohui Xiee8297342015-10-26 19:47:54 +0800138#define CONFIG_SYS_DPAA_FMAN
139#ifdef CONFIG_SYS_DPAA_FMAN
140#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
141
Shaohui Xiee8297342015-10-26 19:47:54 +0800142#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
143#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530144#endif
Shaohui Xiee8297342015-10-26 19:47:54 +0800145
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800146/* Miscellaneous configurable options */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800147
148#define CONFIG_HWCONFIG
149#define HWCONFIG_BUFFER_SIZE 128
150
Sumit Garg4139b172017-03-30 09:52:38 +0530151#ifndef SPL_NO_MISC
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800152#ifndef CONFIG_SPL_BUILD
153#define BOOT_TARGET_DEVICES(func) \
154 func(MMC, mmc, 0) \
Mian Yousaf Kaukab688cdf42019-01-29 16:38:40 +0100155 func(USB, usb, 0) \
156 func(DHCP, dhcp, na)
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800157#include <config_distro_bootcmd.h>
158#endif
159
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800160/* Initial environment variables */
161#define CONFIG_EXTRA_ENV_SETTINGS \
162 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800163 "fdt_high=0xffffffffffffffff\0" \
164 "initrd_high=0xffffffffffffffff\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530165 "kernel_addr=0x61000000\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800166 "scriptaddr=0x80000000\0" \
Sumit Garg76bbf1c2017-06-05 23:51:51 +0530167 "scripthdraddr=0x80080000\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800168 "fdtheader_addr_r=0x80100000\0" \
169 "kernelheader_addr_r=0x80200000\0" \
170 "kernel_addr_r=0x81000000\0" \
Wen Heeb967b92018-11-20 16:55:25 +0800171 "kernel_start=0x1000000\0" \
172 "kernelheader_start=0x800000\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800173 "fdt_addr_r=0x90000000\0" \
174 "load_addr=0xa0000000\0" \
Manish Tomar507103f2020-11-05 14:08:55 +0530175 "kernelheader_addr=0x60600000\0" \
Qianyu Gongad6767b2016-03-15 16:35:57 +0800176 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530177 "kernelheader_size=0x40000\0" \
Shengzhou Liu1c8263d2017-11-09 17:57:55 +0800178 "kernel_addr_sd=0x8000\0" \
179 "kernel_size_sd=0x14000\0" \
Manish Tomar507103f2020-11-05 14:08:55 +0530180 "kernelhdr_addr_sd=0x3000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530181 "kernelhdr_size_sd=0x10\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800182 "console=ttyS0,115200\0" \
York Sun23af4842017-09-28 08:42:16 -0700183 "boot_os=y\0" \
Tom Rini43ede0b2017-10-22 17:55:07 -0400184 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800185 BOOTENV \
186 "boot_scripts=ls1043ardb_boot.scr\0" \
Sumit Garg76bbf1c2017-06-05 23:51:51 +0530187 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800188 "scan_dev_for_boot_part=" \
189 "part list ${devtype} ${devnum} devplist; " \
190 "env exists devplist || setenv devplist 1; " \
191 "for distro_bootpart in ${devplist}; do " \
192 "if fstype ${devtype} " \
193 "${devnum}:${distro_bootpart} " \
194 "bootfstype; then " \
195 "run scan_dev_for_boot; " \
196 "fi; " \
197 "done\0" \
Sumit Garg76bbf1c2017-06-05 23:51:51 +0530198 "boot_a_script=" \
199 "load ${devtype} ${devnum}:${distro_bootpart} " \
200 "${scriptaddr} ${prefix}${script}; " \
201 "env exists secureboot && load ${devtype} " \
202 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai78c58082019-04-23 05:52:17 +0000203 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
204 "env exists secureboot " \
Sumit Garg76bbf1c2017-06-05 23:51:51 +0530205 "&& esbc_validate ${scripthdraddr};" \
206 "source ${scriptaddr}\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800207 "qspi_bootcmd=echo Trying load from qspi..;" \
208 "sf probe && sf read $load_addr " \
Wen He283e4ab2019-11-14 15:08:15 +0800209 "$kernel_start $kernel_size; env exists secureboot " \
210 "&& sf read $kernelheader_addr_r $kernelheader_start " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530211 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
212 "bootm $load_addr#$board\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800213 "nor_bootcmd=echo Trying load from nor..;" \
214 "cp.b $kernel_addr $load_addr " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530215 "$kernel_size; env exists secureboot " \
216 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
217 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
218 "bootm $load_addr#$board\0" \
Wen Heeb967b92018-11-20 16:55:25 +0800219 "nand_bootcmd=echo Trying load from NAND..;" \
220 "nand info; nand read $load_addr " \
221 "$kernel_start $kernel_size; env exists secureboot " \
222 "&& nand read $kernelheader_addr_r $kernelheader_start " \
223 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
224 "bootm $load_addr#$board\0" \
Shengzhou Liu1c8263d2017-11-09 17:57:55 +0800225 "sd_bootcmd=echo Trying load from SD ..;" \
226 "mmcinfo; mmc read $load_addr " \
227 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530228 "env exists secureboot && mmc read $kernelheader_addr_r " \
229 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
230 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liu1c8263d2017-11-09 17:57:55 +0800231 "bootm $load_addr#$board\0"
232
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800233
Rajesh Bhagatf71b5f12018-11-05 18:02:44 +0000234#ifdef CONFIG_TFABOOT
235#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
236 "env exists secureboot && esbc_halt;"
237#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
238 "env exists secureboot && esbc_halt;"
239#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
240 "env exists secureboot && esbc_halt;"
Pankit Garg1f3d7392018-12-27 04:37:53 +0000241#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
242 "env exists secureboot && esbc_halt;"
Sumit Garg4139b172017-03-30 09:52:38 +0530243#endif
Rajesh Bhagatf71b5f12018-11-05 18:02:44 +0000244#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800245
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800246#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
247
Simon Glass457e51c2017-05-17 08:23:10 -0600248#include <asm/arch/soc.h>
249
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800250#endif /* __LS1043A_COMMON_H */