blob: 76626f08181f912729d54ccf05a697203433f801 [file] [log] [blame]
Peter Pearse5ca98812007-11-09 15:24:26 +00001/*
2 * (C) Copyright 2005-2007
3 * Samsung Electronics.
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 *
6 * Derived from omap2420
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26#include <common.h>
Nishanth Menonac6b3622009-10-16 00:06:37 -050027#include <netdev.h>
Peter Pearse5ca98812007-11-09 15:24:26 +000028#include <asm/arch/omap2420.h>
29#include <asm/io.h>
30#include <asm/arch/bits.h>
31#include <asm/arch/mux.h>
32#include <asm/arch/sys_proto.h>
33#include <asm/arch/sys_info.h>
34#include <asm/arch/mem.h>
Peter Pearse5ca98812007-11-09 15:24:26 +000035#include <asm/mach-types.h>
36
37void wait_for_command_complete(unsigned int wd_base);
38
Peter Pearse2db916e2007-11-15 08:45:13 +000039DECLARE_GLOBAL_DATA_PTR;
40
41#define write_config_reg(reg, value) \
42do { \
43 writeb(value, reg); \
44} while (0)
45
46#define mask_config_reg(reg, mask) \
47do { \
48 char value = readb(reg) & ~(mask); \
49 writeb(value, reg); \
50} while (0)
51
Peter Pearse5ca98812007-11-09 15:24:26 +000052/*******************************************************
53 * Routine: delay
54 * Description: spinning delay to use before udelay works
Peter Pearse2db916e2007-11-15 08:45:13 +000055 ******************************************************/
56static inline void delay(unsigned long loops)
57{
58 __asm__("1:\n" "subs %0, %1, #1\n"
59 "bne 1b":"=r" (loops):"0"(loops));
60}
Peter Pearse5ca98812007-11-09 15:24:26 +000061
62/*****************************************
63 * Routine: board_init
64 * Description: Early hardware init.
65 *****************************************/
66int board_init(void)
67{
Peter Pearse5ca98812007-11-09 15:24:26 +000068 gpmc_init(); /* in SRAM or SDRM, finish GPMC */
69
70 gd->bd->bi_arch_number = 919;
71 /* adress of boot parameters */
72 gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
73
74 return 0;
75}
76
77/**********************************************************
78 * Routine: s_init
79 * Description: Does early system init of muxing and clocks.
80 * - Called path is with sram stack.
81 **********************************************************/
82void s_init(void)
83{
Peter Pearse5ca98812007-11-09 15:24:26 +000084 watchdog_init();
85 set_muxconf_regs();
86 delay(100);
87
88 peripheral_enable();
89 icache_enable();
90}
91
92/*******************************************************
93 * Routine: misc_init_r
94 * Description: Init ethernet (done here so udelay works)
Peter Pearse2db916e2007-11-15 08:45:13 +000095 ********************************************************/
Peter Pearse5ca98812007-11-09 15:24:26 +000096int misc_init_r(void)
97{
Peter Pearse5ca98812007-11-09 15:24:26 +000098 return (0);
99}
100
101/****************************************
102 * Routine: watchdog_init
103 * Description: Shut down watch dogs
104 *****************************************/
105void watchdog_init(void)
106{
107 /* There are 4 watch dogs. 1 secure, and 3 general purpose.
108 * The ROM takes care of the secure one. Of the 3 GP ones,
109 * 1 can reset us directly, the other 2 only generate MPU interrupts.
110 */
111 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
112 wait_for_command_complete(WD2_BASE);
113 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
114
115#define MPU_WD_CLOCKED 1
Peter Pearse2db916e2007-11-15 08:45:13 +0000116#if MPU_WD_CLOCKED
117 /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
Peter Pearse5ca98812007-11-09 15:24:26 +0000118 __raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
119 wait_for_command_complete(WD3_BASE);
120 __raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
121
122 __raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
123 wait_for_command_complete(WD4_BASE);
Peter Pearse2db916e2007-11-15 08:45:13 +0000124 __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
125#endif
Peter Pearse5ca98812007-11-09 15:24:26 +0000126}
127
128/******************************************************
129 * Routine: wait_for_command_complete
130 * Description: Wait for posting to finish on watchdog
Peter Pearse2db916e2007-11-15 08:45:13 +0000131 ******************************************************/
132void wait_for_command_complete(unsigned int wd_base)
133{
Peter Pearse5ca98812007-11-09 15:24:26 +0000134 int pending = 1;
135 do {
136 pending = __raw_readl(wd_base + WWPS);
137 } while (pending);
138}
139
140/*******************************************************************
Nishanth Menonac6b3622009-10-16 00:06:37 -0500141 * Routine:board_eth_init
Peter Pearse5ca98812007-11-09 15:24:26 +0000142 * Description: take the Ethernet controller out of reset and wait
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200143 * for the EEPROM load to complete.
Peter Pearse5ca98812007-11-09 15:24:26 +0000144 ******************************************************************/
Nishanth Menonac6b3622009-10-16 00:06:37 -0500145int board_eth_init(bd_t *bis)
Peter Pearse5ca98812007-11-09 15:24:26 +0000146{
Nishanth Menonac6b3622009-10-16 00:06:37 -0500147 int rc = 0;
148#ifdef CONFIG_LAN91C96
Peter Pearse5ca98812007-11-09 15:24:26 +0000149 int cnt = 20;
150
151 __raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
152
153 __raw_writew(0x0, LAN_RESET_REGISTER);
154 do {
155 __raw_writew(0x1, LAN_RESET_REGISTER);
156 udelay(100);
Kyungmin Park47042b32008-07-08 09:08:40 +0900157 if (cnt == 0)
Peter Pearse5ca98812007-11-09 15:24:26 +0000158 goto eth_reset_err_out;
Peter Pearse5ca98812007-11-09 15:24:26 +0000159 --cnt;
160 } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
161
162 cnt = 20;
163
164 do {
165 __raw_writew(0x0, LAN_RESET_REGISTER);
166 udelay(100);
Kyungmin Park47042b32008-07-08 09:08:40 +0900167 if (cnt == 0)
Peter Pearse5ca98812007-11-09 15:24:26 +0000168 goto eth_reset_err_out;
Peter Pearse5ca98812007-11-09 15:24:26 +0000169 --cnt;
170 } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
171 udelay(1000);
172
Peter Pearse2db916e2007-11-15 08:45:13 +0000173 mask_config_reg(ETH_CONTROL_REG, 0x01);
Peter Pearse5ca98812007-11-09 15:24:26 +0000174 udelay(1000);
Nishanth Menonac6b3622009-10-16 00:06:37 -0500175 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
Peter Pearse5ca98812007-11-09 15:24:26 +0000176eth_reset_err_out:
Peter Pearse5ca98812007-11-09 15:24:26 +0000177#endif
Nishanth Menonac6b3622009-10-16 00:06:37 -0500178 return rc;
Peter Pearse5ca98812007-11-09 15:24:26 +0000179}
180
181/**********************************************
182 * Routine: dram_init
183 * Description: sets uboots idea of sdram size
Peter Pearse2db916e2007-11-15 08:45:13 +0000184 **********************************************/
Peter Pearse5ca98812007-11-09 15:24:26 +0000185int dram_init(void)
186{
Wolfgang Denk99e54762011-12-09 12:14:25 +0100187 unsigned int size;
188 u32 mtype, btype;
Peter Pearse5ca98812007-11-09 15:24:26 +0000189#define NOT_EARLY 0
190
191 btype = get_board_type();
192 mtype = get_mem_type();
Peter Pearse5ca98812007-11-09 15:24:26 +0000193
194 display_board_info(btype);
195
196 if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
Peter Pearse2db916e2007-11-15 08:45:13 +0000197 /* init other chip select */
198 do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
Peter Pearse5ca98812007-11-09 15:24:26 +0000199 }
200
Wolfgang Denk99e54762011-12-09 12:14:25 +0100201 size = get_sdr_cs_size(SDRC_CS0_OSET);
Peter Pearse5ca98812007-11-09 15:24:26 +0000202
203 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
Wolfgang Denk99e54762011-12-09 12:14:25 +0100204 gd->bd->bi_dram[0].size = size;
Peter Pearse5ca98812007-11-09 15:24:26 +0000205#if CONFIG_NR_DRAM_BANKS > 1
Wolfgang Denk99e54762011-12-09 12:14:25 +0100206 size = get_sdr_cs_size(SDRC_CS1_OSET);
207
208 gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start +
209 gd->bd->bi_dram[0].size;
210 gd->bd->bi_dram[1].size = size;
Peter Pearse5ca98812007-11-09 15:24:26 +0000211#endif
212
213 return 0;
214}
215
216/**********************************************************
217 * Routine: set_muxconf_regs
218 * Description: Setting up the configuration Mux registers
219 * specific to the hardware
220 *********************************************************/
221void set_muxconf_regs(void)
222{
223 muxSetupSDRC();
224 muxSetupGPMC();
225 muxSetupUsb0(); /* USB Device */
226 muxSetupUsbHost(); /* USB Host */
227 muxSetupUART1();
228 muxSetupLCD();
229 muxSetupMMCSD();
230 muxSetupTouchScreen();
231}
232
233/*****************************************************************
234 * Routine: peripheral_enable
235 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
Peter Pearse2db916e2007-11-15 08:45:13 +0000236 ******************************************************************/
Peter Pearse5ca98812007-11-09 15:24:26 +0000237void peripheral_enable(void)
238{
239 unsigned int v, if_clks = 0, func_clks = 0;
240
241 /* Enable GP2 timer. */
242 if_clks |= BIT4 | BIT3;
243 func_clks |= BIT4 | BIT3;
Peter Pearse2db916e2007-11-15 08:45:13 +0000244 /* Sys_clk input OMAP2420_GPT2 */
245 v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;
Peter Pearse5ca98812007-11-09 15:24:26 +0000246 __raw_writel(v, CM_CLKSEL2_CORE);
247 __raw_writel(0x1, CM_CLKSEL_WKUP);
248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#ifdef CONFIG_SYS_NS16550
Peter Pearse5ca98812007-11-09 15:24:26 +0000250 /* Enable UART1 clock */
251 func_clks |= BIT21;
252 if_clks |= BIT21;
253#endif
Peter Pearse2db916e2007-11-15 08:45:13 +0000254 /* Interface clocks on */
255 v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;
Peter Pearse5ca98812007-11-09 15:24:26 +0000256 __raw_writel(v, CM_ICLKEN1_CORE);
Peter Pearse2db916e2007-11-15 08:45:13 +0000257 /* Functional Clocks on */
258 v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;
Peter Pearse5ca98812007-11-09 15:24:26 +0000259 __raw_writel(v, CM_FCLKEN1_CORE);
260 delay(1000);
261
262#ifndef KERNEL_UPDATED
263 {
264#define V1 0xffffffff
265#define V2 0x00000007
266
267 __raw_writel(V1, CM_FCLKEN1_CORE);
268 __raw_writel(V2, CM_FCLKEN2_CORE);
269 __raw_writel(V1, CM_ICLKEN1_CORE);
270 __raw_writel(V1, CM_ICLKEN2_CORE);
271 }
272#endif
273}
274
275/****************************************
Peter Pearse2db916e2007-11-15 08:45:13 +0000276 * Routine: muxSetupUsb0 (ostboot)
Peter Pearse5ca98812007-11-09 15:24:26 +0000277 * Description: Setup usb muxing
278 *****************************************/
279void muxSetupUsb0(void)
280{
Peter Pearse2db916e2007-11-15 08:45:13 +0000281 mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f);
282 mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f);
283 mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f);
284 mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f);
285 mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f);
286 mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f);
287 mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f);
Peter Pearse5ca98812007-11-09 15:24:26 +0000288}
289
Peter Pearse5ca98812007-11-09 15:24:26 +0000290/****************************************
Peter Pearse2db916e2007-11-15 08:45:13 +0000291 * Routine: muxSetupUSBHost (ostboot)
Peter Pearse5ca98812007-11-09 15:24:26 +0000292 * Description: Setup USB Host muxing
293 *****************************************/
294void muxSetupUsbHost(void)
295{
Peter Pearse5ca98812007-11-09 15:24:26 +0000296 /* V19 */
Peter Pearse2db916e2007-11-15 08:45:13 +0000297 write_config_reg(CONTROL_PADCONF_USB1_RCV, 1);
Peter Pearse5ca98812007-11-09 15:24:26 +0000298 /* W20 */
Peter Pearse2db916e2007-11-15 08:45:13 +0000299 write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1);
Peter Pearse5ca98812007-11-09 15:24:26 +0000300 /* N14 */
Peter Pearse2db916e2007-11-15 08:45:13 +0000301 write_config_reg(CONTROL_PADCONF_GPIO69, 3);
Peter Pearse5ca98812007-11-09 15:24:26 +0000302 /* P15 */
Peter Pearse2db916e2007-11-15 08:45:13 +0000303 write_config_reg(CONTROL_PADCONF_GPIO70, 3);
Peter Pearse5ca98812007-11-09 15:24:26 +0000304 /* L18 */
Peter Pearse2db916e2007-11-15 08:45:13 +0000305 write_config_reg(CONTROL_PADCONF_GPIO102, 3);
Peter Pearse5ca98812007-11-09 15:24:26 +0000306 /* L19 */
Peter Pearse2db916e2007-11-15 08:45:13 +0000307 write_config_reg(CONTROL_PADCONF_GPIO103, 3);
Peter Pearse5ca98812007-11-09 15:24:26 +0000308 /* K15 */
Peter Pearse2db916e2007-11-15 08:45:13 +0000309 write_config_reg(CONTROL_PADCONF_GPIO104, 3);
Peter Pearse5ca98812007-11-09 15:24:26 +0000310 /* K14 */
Peter Pearse2db916e2007-11-15 08:45:13 +0000311 write_config_reg(CONTROL_PADCONF_GPIO105, 3);
Peter Pearse5ca98812007-11-09 15:24:26 +0000312}
313
314/****************************************
Peter Pearse2db916e2007-11-15 08:45:13 +0000315 * Routine: muxSetupUART1 (ostboot)
Peter Pearse5ca98812007-11-09 15:24:26 +0000316 * Description: Set up uart1 muxing
317 *****************************************/
318void muxSetupUART1(void)
319{
Peter Pearse2db916e2007-11-15 08:45:13 +0000320 /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
321 write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
322 /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
323 write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
324 /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
325 write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
326 /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
327 write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
Peter Pearse5ca98812007-11-09 15:24:26 +0000328}
329
330/****************************************
Peter Pearse2db916e2007-11-15 08:45:13 +0000331 * Routine: muxSetupLCD (ostboot)
Peter Pearse5ca98812007-11-09 15:24:26 +0000332 * Description: Setup lcd muxing
333 *****************************************/
334void muxSetupLCD(void)
335{
Peter Pearse2db916e2007-11-15 08:45:13 +0000336 /* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */
337 write_config_reg(CONTROL_PADCONF_DSS_D0, 0);
338 /* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */
339 write_config_reg(CONTROL_PADCONF_DSS_D1, 0);
340 /* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */
341 write_config_reg(CONTROL_PADCONF_DSS_D2, 0);
342 /* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */
343 write_config_reg(CONTROL_PADCONF_DSS_D3, 0);
344 /* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */
345 write_config_reg(CONTROL_PADCONF_DSS_D4, 0);
346 /* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */
347 write_config_reg(CONTROL_PADCONF_DSS_D5, 0);
348 /* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */
349 write_config_reg(CONTROL_PADCONF_DSS_D6, 0);
350 /* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */
351 write_config_reg(CONTROL_PADCONF_DSS_D7, 0);
352 /* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */
353 write_config_reg(CONTROL_PADCONF_DSS_D8, 0);
354 /* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */
355 write_config_reg(CONTROL_PADCONF_DSS_D9, 0);
356 /* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */
357 write_config_reg(CONTROL_PADCONF_DSS_D10, 0);
358 /* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */
359 write_config_reg(CONTROL_PADCONF_DSS_D11, 0);
360 /* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */
361 write_config_reg(CONTROL_PADCONF_DSS_D12, 0);
362 /* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */
363 write_config_reg(CONTROL_PADCONF_DSS_D13, 0);
364 /* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */
365 write_config_reg(CONTROL_PADCONF_DSS_D14, 0);
366 /* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */
367 write_config_reg(CONTROL_PADCONF_DSS_D15, 0);
368 /* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */
369 write_config_reg(CONTROL_PADCONF_DSS_D16, 0);
370 /* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */
371 write_config_reg(CONTROL_PADCONF_DSS_D17, 0);
372 /* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */
373 write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0);
374 /* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */
375 write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0);
376 /* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */
377 write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0);
378 /* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */
379 write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0);
Peter Pearse5ca98812007-11-09 15:24:26 +0000380}
381
382/****************************************
383 * Routine: muxSetupMMCSD (ostboot)
384 * Description: set up MMC muxing
385 *****************************************/
386void muxSetupMMCSD(void)
387{
Peter Pearse2db916e2007-11-15 08:45:13 +0000388 /* SDMMC_CLKI pin configuration, PIN = H15, Mode = 0, PUPD=Disabled */
389 write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0);
390 /* SDMMC_CLKO pin configuration, PIN = G19, Mode = 0, PUPD=Disabled */
391 write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0);
392 /* SDMMC_CMD pin configuration, PIN = H18, Mode = 0, PUPD=Disabled */
393 write_config_reg(CONTROL_PADCONF_MMC_CMD, 0);
394 /* SDMMC_DAT0 pin configuration, PIN = F20, Mode = 0, PUPD=Disabled */
395 write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0);
396 /* SDMMC_DAT1 pin configuration, PIN = H14, Mode = 0, PUPD=Disabled */
397 write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0);
398 /* SDMMC_DAT2 pin configuration, PIN = E19, Mode = 0, PUPD=Disabled */
399 write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0);
400 /* SDMMC_DAT3 pin configuration, PIN = D19, Mode = 0, PUPD=Disabled */
401 write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0);
402 /* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */
403 write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0);
404 /* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */
405 write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0);
406 /* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */
407 write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0);
408 /* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */
409 write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0);
410 /* SDMMC_CDIR pin configuration, PIN = G18, Mode = 0, PUPD=Disabled */
411 write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0);
Peter Pearse5ca98812007-11-09 15:24:26 +0000412}
413
414/******************************************
415 * Routine: muxSetupTouchScreen (ostboot)
Peter Pearse2db916e2007-11-15 08:45:13 +0000416 * Description: Set up touch screen muxing
417 *******************************************/
Peter Pearse5ca98812007-11-09 15:24:26 +0000418void muxSetupTouchScreen(void)
419{
Peter Pearse2db916e2007-11-15 08:45:13 +0000420 /* SPI1_CLK pin configuration, PIN = U18, Mode = 0, PUPD=Disabled */
421 write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0);
422 /* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */
423 write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0);
424 /* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */
425 write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0);
426 /* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */
427 write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0);
Peter Pearse5ca98812007-11-09 15:24:26 +0000428#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1
Peter Pearse2db916e2007-11-15 08:45:13 +0000429 /* PEN_IRQ pin configuration, PIN = N15, Mode = 3, PUPD=Disabled */
430 write_config_reg(CONTROL_PADCONF_GPIO85, 3);
Peter Pearse5ca98812007-11-09 15:24:26 +0000431}
432
433/***************************************************************
434 * Routine: muxSetupGPMC (ostboot)
435 * Description: Configures balls which cam up in protected mode
Peter Pearse2db916e2007-11-15 08:45:13 +0000436 ***************************************************************/
Peter Pearse5ca98812007-11-09 15:24:26 +0000437void muxSetupGPMC(void)
438{
Peter Pearse2db916e2007-11-15 08:45:13 +0000439 /* gpmc_io_dir, MCR */
Kyungmin Park751b9b52008-01-17 16:43:25 +0900440 volatile unsigned int *MCR = (unsigned int *) 0x4800008C;
441 *MCR = 0x19000000;
Peter Pearse5ca98812007-11-09 15:24:26 +0000442
443 /* NOR FLASH CS0 */
Peter Pearse2db916e2007-11-15 08:45:13 +0000444 /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
445 write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0);
Peter Pearse5ca98812007-11-09 15:24:26 +0000446 /* MPDB(Multi Port Debug Port) CS1 */
Peter Pearse2db916e2007-11-15 08:45:13 +0000447 /* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */
448 write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0);
449 /* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */
450 write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0);
451 /* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */
452 write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0);
453 /* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */
454 write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0);
455 /* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */
456 write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0);
457 /* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */
458 write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0);
459 /* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */
460 write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0);
Peter Pearse5ca98812007-11-09 15:24:26 +0000461}
462
463/****************************************************************
Peter Pearse2db916e2007-11-15 08:45:13 +0000464 * Routine: muxSetupSDRC (ostboot)
Peter Pearse5ca98812007-11-09 15:24:26 +0000465 * Description: Configures balls which come up in protected mode
Peter Pearse2db916e2007-11-15 08:45:13 +0000466 ****************************************************************/
Peter Pearse5ca98812007-11-09 15:24:26 +0000467void muxSetupSDRC(void)
468{
469 /* It's set by IPL */
470}