blob: 077e0d0f96fd931fb16c137296e0c285cc59996e [file] [log] [blame]
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +02001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * Copyright (C) 2011 Matrix Vision GmbH
5 * Andre Schwarz <andre.schwarz@matrix-vision.de>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26#include <version.h>
27
28/*
29 * High Level Configuration Options
30 */
31#define CONFIG_E300 1
32#define CONFIG_MPC83xx 1
33#define CONFIG_MPC837x 1
34#define CONFIG_MPC8377 1
35
36#define CONFIG_SYS_TEXT_BASE 0xFC000000
37
38#define CONFIG_PCI 1
39
40#define CONFIG_MASK_AER_AO
41#define CONFIG_DISPLAY_AER_FULL
42
43#define CONFIG_MISC_INIT_R
44
45/*
46 * On-board devices
47 */
48#define CONFIG_TSEC_ENET
49
50/*
51 * System Clock Setup
52 */
53#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
54#define CONFIG_PCIE
55#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
56#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
57
58/*
59 * Hardware Reset Configuration Word stored in EEPROM.
60 */
61#define CONFIG_SYS_HRCW_LOW 0
62#define CONFIG_SYS_HRCW_HIGH 0
63
64/* Arbiter Configuration Register */
65#define CONFIG_SYS_ACR_PIPE_DEP 3
66#define CONFIG_SYS_ACR_RPTCNT 3
67
68/* System Priority Control Regsiter */
69#define CONFIG_SYS_SPCR_TSECEP 3
70
71/* System Clock Configuration Register */
72#define CONFIG_SYS_SCCR_TSEC1CM 3
73#define CONFIG_SYS_SCCR_TSEC2CM 0
74#define CONFIG_SYS_SCCR_SDHCCM 3
75#define CONFIG_SYS_SCCR_ENCCM 3 /* also clock for I2C-1 */
76#define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM /* must match */
77#define CONFIG_SYS_SCCR_PCIEXP1CM 3
78#define CONFIG_SYS_SCCR_PCIEXP2CM 3
79#define CONFIG_SYS_SCCR_PCICM 1
80#define CONFIG_SYS_SCCR_SATACM 0xFF
81
82/*
83 * System IO Config
84 */
85#define CONFIG_SYS_SICRH 0x087c0000
86#define CONFIG_SYS_SICRL 0x40000000
87
88/*
89 * Output Buffer Impedance
90 */
91#define CONFIG_SYS_OBIR 0x30000000
92
93/*
94 * IMMR new address
95 */
96#define CONFIG_SYS_IMMR 0xE0000000
97
98/*
99 * DDR Setup
100 */
101#define CONFIG_SYS_DDR_BASE 0x00000000
102#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
103#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
104#define CONFIG_SYS_83XX_DDR_USES_CS0
105
106#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN | DDRCDR_PZ_HIZ |\
107 DDRCDR_NZ_HIZ | DDRCDR_ODT |\
108 DDRCDR_Q_DRN)
109
110#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
111
112#define CONFIG_SYS_DDR_MODE_WEAK
113#define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2
114#define CONFIG_SYS_DDR_CPO 0x1f
115
116/* SPD table located at offset 0x20 in extended adressing ROM
117 * used for HRCW fetch after power-on reset
118 */
119#define CONFIG_SPD_EEPROM
120#define SPD_EEPROM_ADDRESS 0x50
121#define SPD_EEPROM_OFFSET 0x20
122#define SPD_EEPROM_ADDR_LEN 2
123
124/*
125 * The reserved memory
126 */
127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
128#define CONFIG_SYS_MONITOR_LEN (512*1024)
129#define CONFIG_SYS_MALLOC_LEN (512*1024)
130
131/*
132 * Initial RAM Base Address Setup
133 */
134#define CONFIG_SYS_INIT_RAM_LOCK 1
135#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
136#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
137#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
138#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
139 CONFIG_SYS_GBL_DATA_SIZE)
140
141/*
142 * Local Bus Configuration & Clock Setup
143 */
144#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
145#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
146#define CONFIG_SYS_LBC_LBCR 0x00000000
147#define CONFIG_FSL_ELBC 1
148
149/*
150 * FLASH on the Local Bus
151 */
152#define CONFIG_SYS_FLASH_CFI
153#define CONFIG_FLASH_CFI_DRIVER
154#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
155
156#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
157#define CONFIG_SYS_FLASH_SIZE 64
158
159#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
160#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
161
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500162#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
163 BR_MS_GPCM | BR_V)
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200164#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
165 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500166 OR_GPCM_XACS | OR_GPCM_SCY_15 |\
167 OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
168 OR_GPCM_EAD)
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200169
170#define CONFIG_SYS_MAX_FLASH_BANKS 1
171#define CONFIG_SYS_MAX_FLASH_SECT 512
172
173#undef CONFIG_SYS_FLASH_CHECKSUM
174#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (ms) */
175#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
176
177/*
178 * NAND Flash on the Local Bus
179 */
180#define CONFIG_MTD_NAND_VERIFY_WRITE 1
181#define CONFIG_SYS_MAX_NAND_DEVICE 1
Joe Hershberger7c3a4f92011-10-11 23:57:08 -0500182#define CONFIG_NAND_FSL_ELBC 1
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200183
184#define CONFIG_SYS_NAND_BASE 0xE0600000
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500185#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200186 BR_PS_8 | BR_MS_FCM | BR_V)
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500187#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200188 OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
189 OR_FCM_TRLX | OR_FCM_EHTR)
190
191#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500192#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200193
194/*
195 * Serial Port
196 */
197#define CONFIG_CONS_INDEX 1
198#define CONFIG_SYS_NS16550
199#define CONFIG_SYS_NS16550_SERIAL
200#define CONFIG_SYS_NS16550_REG_SIZE 1
201#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
202
203#define CONFIG_SYS_BAUDRATE_TABLE \
204 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
205
206#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
207#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
208
209#define CONFIG_CONSOLE ttyS0
210#define CONFIG_BAUDRATE 115200
211
212/* SERDES */
213#define CONFIG_FSL_SERDES
214#define CONFIG_FSL_SERDES1 0xe3000
215#define CONFIG_FSL_SERDES2 0xe3100
216
217/* Use the HUSH parser */
218#define CONFIG_SYS_HUSH_PARSER
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200219
220/* Pass open firmware flat tree */
221#define CONFIG_OF_LIBFDT 1
222#define CONFIG_OF_BOARD_SETUP 1
223#define CONFIG_OF_STDOUT_VIA_ALIAS 1
224
225/* I2C */
226#define CONFIG_HARD_I2C
227#define CONFIG_FSL_I2C
228#define CONFIG_I2C_MULTI_BUS
229#define CONFIG_SYS_I2C_SPEED 120000
230#define CONFIG_SYS_I2C_SLAVE 0x7F
231#define CONFIG_SYS_I2C_OFFSET 0x3000
232#define CONFIG_SYS_I2C2_OFFSET 0x3100
233
234/*
235 * General PCI
236 * Addresses are mapped 1-1.
237 */
238#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
239#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
240#define CONFIG_SYS_PCI_MEM_SIZE (256 << 20)
241#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
242#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
243#define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20)
244#define CONFIG_SYS_PCI_IO_BASE 0x00000000
245#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
246#define CONFIG_SYS_PCI_IO_SIZE (1 << 20)
247
248#ifdef CONFIG_PCIE
249#define CONFIG_SYS_PCIE1_BASE 0xA0000000
250#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
251#define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20)
252#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
253#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
254#define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20)
255#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
256#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
257#define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20)
258
259#define CONFIG_SYS_PCIE2_BASE 0xC0000000
260#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
261#define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20)
262#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
263#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
264#define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20)
265#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
266#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
267#define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20)
268#endif
269
270#define CONFIG_PCI_PNP
271#define CONFIG_PCI_SCAN_SHOW
272#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
273
274/*
275 * TSEC
276 */
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200277#define CONFIG_GMII /* MII PHY management */
278#define CONFIG_SYS_VSC8601_SKEWFIX
279#define CONFIG_SYS_VSC8601_SKEW_TX 3
280#define CONFIG_SYS_VSC8601_SKEW_RX 3
281
282#define CONFIG_TSEC1
283#define CONFIG_HAS_ETH0
284#define CONFIG_TSEC1_NAME "TSEC0"
285#define CONFIG_SYS_TSEC1_OFFSET 0x24000
286#define TSEC1_PHY_ADDR 0x10
287#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
288#define TSEC1_PHYIDX 0
289
290#define CONFIG_ETHPRIME "TSEC0"
291#define CONFIG_HAS_ETH0
292
293/*
294 * SATA
295 */
296#define CONFIG_LIBATA
297#define CONFIG_FSL_SATA
298
299#define CONFIG_SYS_SATA_MAX_DEVICE 2
300#define CONFIG_SATA1
301#define CONFIG_SYS_SATA1_OFFSET 0x18000
302#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
303#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
304#define CONFIG_SATA2
305#define CONFIG_SYS_SATA2_OFFSET 0x19000
306#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
307#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
308
309#define CONFIG_LBA48
310#define CONFIG_CMD_SATA
311#define CONFIG_DOS_PARTITION
312#define CONFIG_CMD_EXT2
313
314/*
315 * BOOTP options
316 */
317#define CONFIG_BOOTP_BOOTFILESIZE
318#define CONFIG_BOOTP_BOOTPATH
319#define CONFIG_BOOTP_GATEWAY
320#define CONFIG_BOOTP_HOSTNAME
321#define CONFIG_BOOTP_VENDOREX
322#define CONFIG_BOOTP_SUBNETMASK
323#define CONFIG_BOOTP_DNS
324#define CONFIG_BOOTP_DNS2
325#define CONFIG_BOOTP_NTPSERVER
326#define CONFIG_BOOTP_RANDOM_DELAY
327#define CONFIG_BOOTP_SEND_HOSTNAME
328
329/*
330 * Command line configuration.
331 */
332#include <config_cmd_default.h>
333
334#define CONFIG_CMD_ASKENV
335#define CONFIG_CMD_NAND
336#define CONFIG_CMD_PING
337#define CONFIG_CMD_EEPROM
338#define CONFIG_CMD_I2C
339#define CONFIG_CMD_MII
340#define CONFIG_CMD_PCI
341#define CONFIG_CMD_USB
342#define CONFIG_CMD_SPI
343#define CONFIG_CMD_DHCP
344#define CONFIG_CMD_UBI
345#define CONFIG_CMD_UBIFS
346#define CONFIG_CMD_MTDPARTS
347#define CONFIG_CMD_SATA
348
349#define CONFIG_CMD_EXT2
350#define CONFIG_CMD_FAT
351#define CONFIG_CMD_JFFS2
352
353#define CONFIG_RBTREE
354#define CONFIG_LZO
355
356#define CONFIG_MTD_DEVICE
357#define CONFIG_MTD_PARTITIONS
358
359#define CONFIG_FLASH_CFI_MTD
360#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
361#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
362
363#define CONFIG_FIT
364#define CONFIG_FIT_VERBOSE 1
365
366#define CONFIG_CMDLINE_EDITING 1
367#define CONFIG_AUTO_COMPLETE
368
369/*
370 * Miscellaneous configurable options
371 */
372#define CONFIG_SYS_LONGHELP
373#define CONFIG_SYS_LOAD_ADDR 0x2000000
374#define CONFIG_LOADADDR 0x4000000
375#define CONFIG_SYS_PROMPT "=> "
376#define CONFIG_SYS_CBSIZE 256
377
378#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
379#define CONFIG_SYS_MAXARGS 16
380#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
381#define CONFIG_SYS_HZ 1000
382
383#define CONFIG_LOADS_ECHO 1
384#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
385
386#define CONFIG_SYS_MEMTEST_START (60<<20)
387#define CONFIG_SYS_MEMTEST_END (70<<20)
388
389/*
390 * For booting Linux, the board info and command line data
391 * have to be in the first 256 MB of memory, since this is
392 * the maximum mapped by the Linux kernel during initialization.
393 */
394#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
395
396/*
397 * Core HID Setup
398 */
399#define CONFIG_SYS_HID0_INIT 0x000000000
400#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
401 HID0_ENABLE_INSTRUCTION_CACHE)
402#define CONFIG_SYS_HID2 HID2_HBE
403
404/*
405 * MMU Setup
406 */
407#define CONFIG_HIGH_BATS 1
408
409/* DDR: cache cacheable */
410#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE
411
Joe Hershberger72cd4082011-10-11 23:57:28 -0500412#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200413 BATL_MEMCOHERENCE)
414#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
415 BATU_VP)
416#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
417#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
418
419/* unused */
420#define CONFIG_SYS_IBAT1L (0)
421#define CONFIG_SYS_IBAT1U (0)
422#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
423#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
424
425/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500426#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200427 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
428#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
429 BATU_VP)
430#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
431#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
432
433/* unused */
434#define CONFIG_SYS_IBAT3L (0)
435#define CONFIG_SYS_IBAT3U (0)
436#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
437#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
438
439/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500440#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200441 BATL_MEMCOHERENCE)
442#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
443 BATU_VS | BATU_VP)
Joe Hershberger72cd4082011-10-11 23:57:28 -0500444#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200445 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
446#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
447
448/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500449#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200450#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
451 BATU_VS | BATU_VP)
452#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
453#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
454
455/* PCI MEM space: cacheable */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500456#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200457 BATL_MEMCOHERENCE)
458#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
459 BATU_VS | BATU_VP)
460#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
461#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
462
463/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500464#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200465 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
466#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
467 BATU_VS | BATU_VP)
468#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
469#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
470
471/*
472 * I2C EEPROM settings
473 */
474#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
475#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
476#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Joe Hershberger7c3a4f92011-10-11 23:57:08 -0500477#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200478#define CONFIG_SYS_EEPROM_SIZE 0x4000
479
480/*
481 * Environment Configuration
482 */
483#define CONFIG_SYS_FLASH_PROTECTION
484#define CONFIG_ENV_OVERWRITE
485#define CONFIG_ENV_IS_IN_FLASH 1
486#define CONFIG_ENV_ADDR 0xFFD00000
487#define CONFIG_ENV_SECT_SIZE 0x20000
488#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
489
490/*
491 * Video
492 */
493#define CONFIG_VIDEO
494#define CONFIG_VIDEO_SM501_PCI
495#define VIDEO_FB_LITTLE_ENDIAN
496#define CONFIG_CMD_BMP
497#define CONFIG_VIDEO_SM501
498#define CONFIG_VIDEO_SM501_32BPP
499#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
500#define CONFIG_CFB_CONSOLE
501#define CONFIG_VIDEO_LOGO
502#define CONFIG_VIDEO_BMP_LOGO
503#define CONFIG_VGA_AS_SINGLE_DEVICE
504#define CONFIG_SPLASH_SCREEN
505#define CONFIG_SYS_CONSOLE_IS_IN_ENV
506#define CONFIG_VIDEO_BMP_GZIP
507#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
508
509/*
510 * SPI
511 */
512#define CONFIG_MPC8XXX_SPI
513
514/*
515 * USB
516 */
517#define CONFIG_SYS_USB_HOST
518#define CONFIG_USB_EHCI
519#define CONFIG_USB_EHCI_FSL
520#define CONFIG_HAS_FSL_DR_USB
521#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
522
523#define CONFIG_USB_STORAGE
524#define CONFIG_USB_KEYBOARD
525/*
526 *
527 */
528#define CONFIG_BOOTDELAY 5
529#define CONFIG_AUTOBOOT_KEYED
530#define CONFIG_AUTOBOOT_STOP_STR "s"
531#define CONFIG_ZERO_BOOTDELAY_CHECK
532#define CONFIG_RESET_TO_RETRY 1000
533
Joe Hershberger7c3a4f92011-10-11 23:57:08 -0500534#define MV_CI "MergerBox"
535#define MV_VCI "MergerBox"
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200536#define MV_FPGA_DATA 0xfc100000
537#define MV_FPGA_SIZE 0x00200000
538
539#define CONFIG_SHOW_BOOT_PROGRESS 1
540
541#define MV_KERNEL_ADDR_RAM 0x02800000
542#define MV_DTB_ADDR_RAM 0x00600000
543#define MV_INITRD_ADDR_RAM 0x01000000
544#define MV_FITADDR 0xfc300000
545#define MV_SPLAH_ADDR 0xffe00000
546
547#define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\
548 "then; run fitboot;else;run ubiboot;fi;"
549#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
550
551#define XMK_STR(x) #x
552#define MK_STR(x) XMK_STR(x)
553
554#define CONFIG_EXTRA_ENV_SETTINGS \
555 "console_nr=0\0"\
556 "stdin=serial\0"\
557 "stdout=serial\0"\
558 "stderr=serial\0"\
559 "boot_sqfs=1\0"\
560 "usb_dr_mode=host\0"\
561 "bootfile=MergerBox.fit\0"\
562 "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"\
563 "fpga=0\0"\
564 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"\
565 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"\
566 "mv_kernel_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"\
567 "mv_initrd_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"\
568 "mv_dtb_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"\
569 "uboota=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"\
570 "fitaddr=" MK_STR(MV_FITADDR) "\0"\
571 "mv_version=" U_BOOT_VERSION "\0"\
572 "mtdids=" MTDIDS_DEFAULT "\0"\
573 "mtdparts=" MTDPARTS_DEFAULT "\0"\
Joe Hershberger7c3a4f92011-10-11 23:57:08 -0500574 "dhcp_client_id=" MV_CI "\0"\
575 "dhcp_vendor-class-identifier=" MV_VCI "\0"\
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +0200576 "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
577 "protect off all;erase $uboota +0xC0000;"\
578 "cp.b $loadaddr $uboota $filesize\0"\
579 "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
580 "cp.b $loadaddr $fpgadata $filesize\0"\
581 "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
582 "cp.b $loadaddr $fitaddr $filesize\0"\
583 "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
584 "rootfstype=squashfs\0"\
585 "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
586 "rootfstype=ubifs\0"\
587 "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
588 "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
589 "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
590 "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
591 "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
592 "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
593 "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
594 "imxtract $fitaddr ramdisk $mv_initrd_ram;"\
595 "imxtract $fitaddr fdt $mv_dtb_ram\0"\
596 "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
597 "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
598 "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
599 "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
600 "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
601 "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
602 "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
603 "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
604 "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
605 "splashimage=" MK_STR(MV_SPLAH_ADDR) "\0"\
606 ""
607
608#undef MK_STR
609#undef XMK_STR
610
611/*
612 * FPGA
613 */
614#define CONFIG_FPGA_COUNT 1
615#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
616#define CONFIG_FPGA_ALTERA
617#define CONFIG_FPGA_CYCLON2
618
619#endif