blob: 619b287258f7185a38dcad2db01b3da38106a424 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Shengzhou Liu8d67c362014-03-05 15:04:48 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Biwen Li8e4be6d2020-05-01 20:04:19 +08004 * Copyright 2020 NXP
Shengzhou Liu8d67c362014-03-05 15:04:48 +08005 */
6
7/*
8 * T2080 RDB/PCIe board configuration file
9 */
10
11#ifndef __T2080RDB_H
12#define __T2080RDB_H
13
Shengzhou Liu8d67c362014-03-05 15:04:48 +080014#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
Shengzhou Liu8d67c362014-03-05 15:04:48 +080015#define CONFIG_FSL_SATA_V2
16
17/* High Level Configuration Options */
Shengzhou Liu8d67c362014-03-05 15:04:48 +080018#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Shengzhou Liu8d67c362014-03-05 15:04:48 +080019#define CONFIG_ENABLE_36BIT_PHYS
20
21#ifdef CONFIG_PHYS_64BIT
22#define CONFIG_ADDR_MAP 1
23#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
24#endif
25
26#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
York Sun51370d52016-12-28 08:43:45 -080027#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
Shengzhou Liu8d67c362014-03-05 15:04:48 +080028#define CONFIG_ENV_OVERWRITE
29
30#ifdef CONFIG_RAMBOOT_PBL
Masahiro Yamadae4536f82014-03-11 11:05:16 +090031#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
Shengzhou Liu4d666682014-04-18 16:43:40 +080032
Shengzhou Liu4d666682014-04-18 16:43:40 +080033#define CONFIG_SPL_FLUSH_IMAGE
Shengzhou Liu4d666682014-04-18 16:43:40 +080034#define CONFIG_SPL_PAD_TO 0x40000
35#define CONFIG_SPL_MAX_SIZE 0x28000
36#define RESET_VECTOR_OFFSET 0x27FFC
37#define BOOT_PAGE_OFFSET 0x27000
38#ifdef CONFIG_SPL_BUILD
39#define CONFIG_SPL_SKIP_RELOCATE
40#define CONFIG_SPL_COMMON_INIT_DDR
41#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Shengzhou Liu8d67c362014-03-05 15:04:48 +080042#endif
43
Miquel Raynal88718be2019-10-03 19:50:03 +020044#ifdef CONFIG_MTD_RAW_NAND
Shengzhou Liu4d666682014-04-18 16:43:40 +080045#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
46#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
47#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
48#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
Zhao Qiangec90ac72016-09-08 12:55:32 +080049#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
Shengzhou Liu4d666682014-04-18 16:43:40 +080050#endif
51
52#ifdef CONFIG_SPIFLASH
53#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liu4d666682014-04-18 16:43:40 +080054#define CONFIG_SPL_SPI_FLASH_MINIMAL
55#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
56#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
57#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
58#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
Shengzhou Liu4d666682014-04-18 16:43:40 +080059#ifndef CONFIG_SPL_BUILD
60#define CONFIG_SYS_MPC85XX_NO_RESETVEC
61#endif
Zhao Qiangec90ac72016-09-08 12:55:32 +080062#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
Shengzhou Liu4d666682014-04-18 16:43:40 +080063#endif
64
65#ifdef CONFIG_SDCARD
66#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liu4d666682014-04-18 16:43:40 +080067#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
68#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
69#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
70#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
Shengzhou Liu4d666682014-04-18 16:43:40 +080071#ifndef CONFIG_SPL_BUILD
72#define CONFIG_SYS_MPC85XX_NO_RESETVEC
73#endif
Zhao Qiangec90ac72016-09-08 12:55:32 +080074#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
Shengzhou Liu4d666682014-04-18 16:43:40 +080075#endif
76
77#endif /* CONFIG_RAMBOOT_PBL */
78
Shengzhou Liu8d67c362014-03-05 15:04:48 +080079#define CONFIG_SRIO_PCIE_BOOT_MASTER
80#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
81/* Set 1M boot space */
82#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
83#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
84 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
85#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Shengzhou Liu8d67c362014-03-05 15:04:48 +080086#endif
87
Shengzhou Liu8d67c362014-03-05 15:04:48 +080088#ifndef CONFIG_RESET_VECTOR_ADDRESS
89#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
90#endif
91
92/*
93 * These can be toggled for performance analysis, otherwise use default.
94 */
95#define CONFIG_SYS_CACHE_STASHING
96#define CONFIG_BTB /* toggle branch predition */
97#define CONFIG_DDR_ECC
98#ifdef CONFIG_DDR_ECC
99#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
100#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
101#endif
102
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800103#if defined(CONFIG_SPIFLASH)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800104#elif defined(CONFIG_SDCARD)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800105#define CONFIG_SYS_MMC_ENV_DEV 0
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800106#endif
107
108#ifndef __ASSEMBLY__
109unsigned long get_board_sys_clk(void);
110unsigned long get_board_ddr_clk(void);
111#endif
112
113#define CONFIG_SYS_CLK_FREQ 66660000
114#define CONFIG_DDR_CLK_FREQ 133330000
115
116/*
117 * Config the L3 Cache as L3 SRAM
118 */
Shengzhou Liu4d666682014-04-18 16:43:40 +0800119#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
120#define CONFIG_SYS_L3_SIZE (512 << 10)
121#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
Tom Rinia09fea12019-11-18 20:02:10 -0500122#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
Shengzhou Liu4d666682014-04-18 16:43:40 +0800123#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
124#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
125#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800126
127#define CONFIG_SYS_DCSRBAR 0xf0000000
128#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
129
130/* EEPROM */
131#define CONFIG_ID_EEPROM
132#define CONFIG_SYS_I2C_EEPROM_NXID
133#define CONFIG_SYS_EEPROM_BUS_NUM 0
134#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
Shengzhou Liuef531c72014-04-18 16:43:41 +0800135#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800136
137/*
138 * DDR Setup
139 */
140#define CONFIG_VERY_BIG_RAM
141#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
142#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
143#define CONFIG_DIMM_SLOTS_PER_CTLR 1
144#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
145#define CONFIG_DDR_SPD
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800146#define CONFIG_SYS_SPD_BUS_NUM 0
147#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
148#define SPD_EEPROM_ADDRESS1 0x51
149#define SPD_EEPROM_ADDRESS2 0x52
150#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
151#define CTRL_INTLV_PREFERED cacheline
152
153/*
154 * IFC Definitions
155 */
156#define CONFIG_SYS_FLASH_BASE 0xe8000000
157#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
158#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
159#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
160 CSPR_PORT_SIZE_16 | \
161 CSPR_MSEL_NOR | \
162 CSPR_V)
163#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
164
165/* NOR Flash Timing Params */
166#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
167
168#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
169 FTIM0_NOR_TEADC(0x5) | \
170 FTIM0_NOR_TEAHC(0x5))
171#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
172 FTIM1_NOR_TRAD_NOR(0x1A) |\
173 FTIM1_NOR_TSEQRAD_NOR(0x13))
174#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
175 FTIM2_NOR_TCH(0x4) | \
176 FTIM2_NOR_TWPH(0x0E) | \
177 FTIM2_NOR_TWP(0x1c))
178#define CONFIG_SYS_NOR_FTIM3 0x0
179
180#define CONFIG_SYS_FLASH_QUIET_TEST
181#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
182
183#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
184#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
185#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
186#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
187#define CONFIG_SYS_FLASH_EMPTY_INFO
188#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
189
190/* CPLD on IFC */
191#define CONFIG_SYS_CPLD_BASE 0xffdf0000
192#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
193#define CONFIG_SYS_CSPR2_EXT (0xf)
194#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
195 | CSPR_PORT_SIZE_8 \
196 | CSPR_MSEL_GPCM \
197 | CSPR_V)
198#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
199#define CONFIG_SYS_CSOR2 0x0
200
201/* CPLD Timing parameters for IFC CS2 */
202#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
203 FTIM0_GPCM_TEADC(0x0e) | \
204 FTIM0_GPCM_TEAHC(0x0e))
205#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
206 FTIM1_GPCM_TRAD(0x1f))
207#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800208 FTIM2_GPCM_TCH(0x8) | \
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800209 FTIM2_GPCM_TWP(0x1f))
210#define CONFIG_SYS_CS2_FTIM3 0x0
211
212/* NAND Flash on IFC */
213#define CONFIG_NAND_FSL_IFC
214#define CONFIG_SYS_NAND_BASE 0xff800000
215#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
216
217#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
218#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
219 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
220 | CSPR_MSEL_NAND /* MSEL = NAND */ \
221 | CSPR_V)
222#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
223
224#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
225 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
226 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
227 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
228 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
229 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
230 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
231
232#define CONFIG_SYS_NAND_ONFI_DETECTION
233
234/* ONFI NAND Flash mode0 Timing Params */
235#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
236 FTIM0_NAND_TWP(0x18) | \
237 FTIM0_NAND_TWCHT(0x07) | \
238 FTIM0_NAND_TWH(0x0a))
239#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
240 FTIM1_NAND_TWBE(0x39) | \
241 FTIM1_NAND_TRR(0x0e) | \
242 FTIM1_NAND_TRP(0x18))
243#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
244 FTIM2_NAND_TREH(0x0a) | \
245 FTIM2_NAND_TWHRE(0x1e))
246#define CONFIG_SYS_NAND_FTIM3 0x0
247
248#define CONFIG_SYS_NAND_DDR_LAW 11
249#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
250#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800251#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
252
Miquel Raynal88718be2019-10-03 19:50:03 +0200253#if defined(CONFIG_MTD_RAW_NAND)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800254#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
255#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
256#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
257#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
258#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
259#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
260#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
261#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
262#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
263#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
264#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
265#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
266#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
267#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
268#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
269#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
270#else
271#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
272#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
273#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
274#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
275#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
276#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
277#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
278#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
279#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
280#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
281#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
282#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
283#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
284#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
285#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
286#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
287#endif
288
289#if defined(CONFIG_RAMBOOT_PBL)
290#define CONFIG_SYS_RAMBOOT
291#endif
292
Shengzhou Liu4d666682014-04-18 16:43:40 +0800293#ifdef CONFIG_SPL_BUILD
294#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
295#else
296#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
297#endif
298
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800299#define CONFIG_HWCONFIG
300
301/* define to use L1 as initial stack */
302#define CONFIG_L1_INIT_RAM
303#define CONFIG_SYS_INIT_RAM_LOCK
304#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
305#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700306#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800307/* The assembler doesn't like typecast */
308#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
309 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
310 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
311#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
312#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
313 GENERATED_GBL_DATA_SIZE)
314#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530315#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800316#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
317
318/*
319 * Serial Port
320 */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800321#define CONFIG_SYS_NS16550_SERIAL
322#define CONFIG_SYS_NS16550_REG_SIZE 1
323#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
324#define CONFIG_SYS_BAUDRATE_TABLE \
325 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
326#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
327#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
328#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
329#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
330
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800331/*
332 * I2C
333 */
Biwen Li8e4be6d2020-05-01 20:04:19 +0800334#ifndef CONFIG_DM_I2C
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800335#define CONFIG_SYS_I2C
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800336#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
337#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
338#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
339#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
340#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
341#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
342#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
343#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
344#define CONFIG_SYS_FSL_I2C_SPEED 100000
345#define CONFIG_SYS_FSL_I2C2_SPEED 100000
346#define CONFIG_SYS_FSL_I2C3_SPEED 100000
347#define CONFIG_SYS_FSL_I2C4_SPEED 100000
Biwen Li8e4be6d2020-05-01 20:04:19 +0800348#else
349#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
350#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
351#endif
352
353#define CONFIG_SYS_I2C_FSL
354
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800355#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
356#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
357#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
358#define I2C_MUX_CH_DEFAULT 0x8
359
Ying Zhange5abb922015-03-10 14:21:36 +0800360#define I2C_MUX_CH_VOL_MONITOR 0xa
361
362#define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
363#ifndef CONFIG_SPL_BUILD
364#define CONFIG_VID
365#endif
366#define CONFIG_VOL_MONITOR_IR36021_SET
367#define CONFIG_VOL_MONITOR_IR36021_READ
368/* The lowest and highest voltage allowed for T208xRDB */
369#define VDD_MV_MIN 819
370#define VDD_MV_MAX 1212
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800371
372/*
373 * RapidIO
374 */
375#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
376#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
377#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
378#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
379#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
380#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
381/*
382 * for slave u-boot IMAGE instored in master memory space,
383 * PHYS must be aligned based on the SIZE
384 */
Liu Gange4911812014-05-15 14:30:34 +0800385#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
386#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
387#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
388#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800389/*
390 * for slave UCODE and ENV instored in master memory space,
391 * PHYS must be aligned based on the SIZE
392 */
Liu Gange4911812014-05-15 14:30:34 +0800393#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800394#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
395#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
396
397/* slave core release by master*/
398#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
399#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
400
401/*
402 * SRIO_PCIE_BOOT - SLAVE
403 */
404#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
405#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
406#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
407 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
408#endif
409
410/*
411 * eSPI - Enhanced SPI
412 */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800413
414/*
415 * General PCI
416 * Memory space is mapped 1-1, but I/O space must start from 0.
417 */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400418#define CONFIG_PCIE1 /* PCIE controller 1 */
419#define CONFIG_PCIE2 /* PCIE controller 2 */
420#define CONFIG_PCIE3 /* PCIE controller 3 */
421#define CONFIG_PCIE4 /* PCIE controller 4 */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800422#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
423/* controller 1, direct to uli, tgtid 3, Base address 20000 */
424#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800425#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800426#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800427#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800428
429/* controller 2, Slot 2, tgtid 2, Base address 201000 */
430#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800431#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800432#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800433#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800434
435/* controller 3, Slot 1, tgtid 1, Base address 202000 */
436#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800437#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800438#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800439#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800440
441/* controller 4, Base address 203000 */
442#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800443#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800444#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800445
446#ifdef CONFIG_PCI
Hou Zhiqiangd85fa792019-08-27 11:02:56 +0000447#if !defined(CONFIG_DM_PCI)
448#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
449#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
450#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
451#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
452#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
453#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
454#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
455#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
456#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
457#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
458#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
459#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
460#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
461#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
462#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
463#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
464#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800465#define CONFIG_PCI_INDIRECT_BRIDGE
Hou Zhiqiangd85fa792019-08-27 11:02:56 +0000466#endif
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800467#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800468#endif
469
470/* Qman/Bman */
471#ifndef CONFIG_NOBQFMAN
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800472#define CONFIG_SYS_BMAN_NUM_PORTALS 18
473#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
474#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
475#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500476#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
477#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
478#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
479#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
480#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
481 CONFIG_SYS_BMAN_CENA_SIZE)
482#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
483#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800484#define CONFIG_SYS_QMAN_NUM_PORTALS 18
485#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
486#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
487#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500488#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
489#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
490#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
491#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
492#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
493 CONFIG_SYS_QMAN_CENA_SIZE)
494#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
495#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800496
497#define CONFIG_SYS_DPAA_FMAN
498#define CONFIG_SYS_DPAA_PME
499#define CONFIG_SYS_PMAN
500#define CONFIG_SYS_DPAA_DCE
501#define CONFIG_SYS_DPAA_RMAN /* RMan */
502#define CONFIG_SYS_INTERLAKEN
503
504/* Default address of microcode for the Linux Fman driver */
505#if defined(CONFIG_SPIFLASH)
506/*
507 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
508 * env, so we got 0x110000.
509 */
Shengzhou Liuef531c72014-04-18 16:43:41 +0800510#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800511#define CONFIG_CORTINA_FW_ADDR 0x120000
512
513#elif defined(CONFIG_SDCARD)
514/*
515 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Shengzhou Liu4d666682014-04-18 16:43:40 +0800516 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
517 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800518 */
Shengzhou Liu4d666682014-04-18 16:43:40 +0800519#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
520#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800521
Miquel Raynal88718be2019-10-03 19:50:03 +0200522#elif defined(CONFIG_MTD_RAW_NAND)
Shengzhou Liu4d666682014-04-18 16:43:40 +0800523#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
524#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800525#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
526/*
527 * Slave has no ucode locally, it can fetch this from remote. When implementing
528 * in two corenet boards, slave's ucode could be stored in master's memory
529 * space, the address can be mapped from slave TLB->slave LAW->
530 * slave SRIO or PCIE outbound window->master inbound window->
531 * master LAW->the ucode address in master's memory space.
532 */
Shengzhou Liuef531c72014-04-18 16:43:41 +0800533#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800534#define CONFIG_CORTINA_FW_ADDR 0xFFE10000
535#else
Shengzhou Liuef531c72014-04-18 16:43:41 +0800536#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800537#define CONFIG_CORTINA_FW_ADDR 0xEFE00000
538#endif
539#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
540#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
541#endif /* CONFIG_NOBQFMAN */
542
543#ifdef CONFIG_SYS_DPAA_FMAN
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800544#define CONFIG_CORTINA_FW_LENGTH 0x40000
545#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
546#define RGMII_PHY2_ADDR 0x02
547#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
548#define CORTINA_PHY_ADDR2 0x0d
549#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
550#define FM1_10GEC4_PHY_ADDR 0x01
551#endif
552
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800553#ifdef CONFIG_FMAN_ENET
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800554#define CONFIG_ETHPRIME "FM1@DTSEC3"
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800555#endif
556
557/*
558 * SATA
559 */
560#ifdef CONFIG_FSL_SATA_V2
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800561#define CONFIG_SYS_SATA_MAX_DEVICE 2
562#define CONFIG_SATA1
563#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
564#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
565#define CONFIG_SATA2
566#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
567#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
568#define CONFIG_LBA48
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800569#endif
570
571/*
572 * USB
573 */
Tom Rini8850c5d2017-05-12 22:33:27 -0400574#ifdef CONFIG_USB_EHCI_HCD
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800575#define CONFIG_USB_EHCI_FSL
576#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800577#define CONFIG_HAS_FSL_DR_USB
578#endif
579
580/*
581 * SDHC
582 */
583#ifdef CONFIG_MMC
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800584#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
585#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
586#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800587#endif
588
589/*
Shengzhou Liu4feac1c2014-04-02 14:28:35 +0800590 * Dynamic MTD Partition support with mtdparts
591 */
Shengzhou Liu4feac1c2014-04-02 14:28:35 +0800592
593/*
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800594 * Environment
595 */
596
597/*
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800598 * Miscellaneous configurable options
599 */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800600#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800601
602/*
603 * For booting Linux, the board info and command line data
604 * have to be in the first 64 MB of memory, since this is
605 * the maximum mapped by the Linux kernel during initialization.
606 */
607#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
608#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
609
610#ifdef CONFIG_CMD_KGDB
611#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
612#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
613#endif
614
615/*
616 * Environment Configuration
617 */
618#define CONFIG_ROOTPATH "/opt/nfsroot"
619#define CONFIG_BOOTFILE "uImage"
620#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
621
622/* default location for tftp and bootm */
623#define CONFIG_LOADADDR 1000000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800624#define __USB_PHY_TYPE utmi
625
626#define CONFIG_EXTRA_ENV_SETTINGS \
627 "hwconfig=fsl_ddr:" \
628 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
629 "bank_intlv=auto;" \
630 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
631 "netdev=eth0\0" \
632 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
633 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
634 "tftpflash=tftpboot $loadaddr $uboot && " \
635 "protect off $ubootaddr +$filesize && " \
636 "erase $ubootaddr +$filesize && " \
637 "cp.b $loadaddr $ubootaddr $filesize && " \
638 "protect on $ubootaddr +$filesize && " \
639 "cmp.b $loadaddr $ubootaddr $filesize\0" \
640 "consoledev=ttyS0\0" \
641 "ramdiskaddr=2000000\0" \
642 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500643 "fdtaddr=1e00000\0" \
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800644 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500645 "bdev=sda3\0"
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800646
647/*
648 * For emulation this causes u-boot to jump to the start of the
649 * proof point app code automatically
650 */
651#define CONFIG_PROOF_POINTS \
652 "setenv bootargs root=/dev/$bdev rw " \
653 "console=$consoledev,$baudrate $othbootargs;" \
654 "cpu 1 release 0x29000000 - - -;" \
655 "cpu 2 release 0x29000000 - - -;" \
656 "cpu 3 release 0x29000000 - - -;" \
657 "cpu 4 release 0x29000000 - - -;" \
658 "cpu 5 release 0x29000000 - - -;" \
659 "cpu 6 release 0x29000000 - - -;" \
660 "cpu 7 release 0x29000000 - - -;" \
661 "go 0x29000000"
662
663#define CONFIG_HVBOOT \
664 "setenv bootargs config-addr=0x60000000; " \
665 "bootm 0x01000000 - 0x00f00000"
666
667#define CONFIG_ALU \
668 "setenv bootargs root=/dev/$bdev rw " \
669 "console=$consoledev,$baudrate $othbootargs;" \
670 "cpu 1 release 0x01000000 - - -;" \
671 "cpu 2 release 0x01000000 - - -;" \
672 "cpu 3 release 0x01000000 - - -;" \
673 "cpu 4 release 0x01000000 - - -;" \
674 "cpu 5 release 0x01000000 - - -;" \
675 "cpu 6 release 0x01000000 - - -;" \
676 "cpu 7 release 0x01000000 - - -;" \
677 "go 0x01000000"
678
679#define CONFIG_LINUX \
680 "setenv bootargs root=/dev/ram rw " \
681 "console=$consoledev,$baudrate $othbootargs;" \
682 "setenv ramdiskaddr 0x02000000;" \
683 "setenv fdtaddr 0x00c00000;" \
684 "setenv loadaddr 0x1000000;" \
685 "bootm $loadaddr $ramdiskaddr $fdtaddr"
686
687#define CONFIG_HDBOOT \
688 "setenv bootargs root=/dev/$bdev rw " \
689 "console=$consoledev,$baudrate $othbootargs;" \
690 "tftp $loadaddr $bootfile;" \
691 "tftp $fdtaddr $fdtfile;" \
692 "bootm $loadaddr - $fdtaddr"
693
694#define CONFIG_NFSBOOTCOMMAND \
695 "setenv bootargs root=/dev/nfs rw " \
696 "nfsroot=$serverip:$rootpath " \
697 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
698 "console=$consoledev,$baudrate $othbootargs;" \
699 "tftp $loadaddr $bootfile;" \
700 "tftp $fdtaddr $fdtfile;" \
701 "bootm $loadaddr - $fdtaddr"
702
703#define CONFIG_RAMBOOTCOMMAND \
704 "setenv bootargs root=/dev/ram rw " \
705 "console=$consoledev,$baudrate $othbootargs;" \
706 "tftp $ramdiskaddr $ramdiskfile;" \
707 "tftp $loadaddr $bootfile;" \
708 "tftp $fdtaddr $fdtfile;" \
709 "bootm $loadaddr $ramdiskaddr $fdtaddr"
710
711#define CONFIG_BOOTCOMMAND CONFIG_LINUX
712
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800713#include <asm/fsl_secure_boot.h>
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530714
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800715#endif /* __T2080RDB_H */