Pankaj Bansal | 1eba723 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
Meenakshi Aggarwal | 69b3894 | 2020-01-10 20:13:19 +0530 | [diff] [blame] | 3 | * Copyright 2018-2020 NXP |
Pankaj Bansal | 1eba723 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __LX2_QDS_H |
| 7 | #define __LX2_QDS_H |
| 8 | |
| 9 | #include "lx2160a_common.h" |
| 10 | |
| 11 | /* Qixis */ |
| 12 | #define QIXIS_XMAP_MASK 0x07 |
| 13 | #define QIXIS_XMAP_SHIFT 5 |
| 14 | #define QIXIS_RST_CTL_RESET_EN 0x30 |
| 15 | #define QIXIS_LBMAP_DFLTBANK 0x00 |
| 16 | #define QIXIS_LBMAP_ALTBANK 0x20 |
| 17 | #define QIXIS_LBMAP_QSPI 0x00 |
| 18 | #define QIXIS_RCW_SRC_QSPI 0xff |
| 19 | #define QIXIS_RST_CTL_RESET 0x31 |
| 20 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
| 21 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 |
| 22 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |
| 23 | #define QIXIS_LBMAP_MASK 0x0f |
| 24 | #define QIXIS_LBMAP_SD |
Meenakshi Aggarwal | bddec1b | 2020-01-23 17:55:10 +0530 | [diff] [blame] | 25 | #define QIXIS_LBMAP_EMMC |
Pankaj Bansal | 1eba723 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 26 | #define QIXIS_RCW_SRC_SD 0x08 |
Meenakshi Aggarwal | bddec1b | 2020-01-23 17:55:10 +0530 | [diff] [blame] | 27 | #define QIXIS_RCW_SRC_EMMC 0x09 |
Pankaj Bansal | 1eba723 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 28 | #define NON_EXTENDED_DUTCFG |
| 29 | #define QIXIS_SDID_MASK 0x07 |
| 30 | #define QIXIS_ESDHC_NO_ADAPTER 0x7 |
| 31 | |
| 32 | /* SYSCLK */ |
| 33 | #define QIXIS_SYSCLK_100 0x0 |
| 34 | #define QIXIS_SYSCLK_125 0x1 |
| 35 | #define QIXIS_SYSCLK_133 0x2 |
| 36 | |
| 37 | /* DDRCLK */ |
| 38 | #define QIXIS_DDRCLK_100 0x0 |
| 39 | #define QIXIS_DDRCLK_125 0x1 |
| 40 | #define QIXIS_DDRCLK_133 0x2 |
| 41 | |
| 42 | #define BRDCFG4_EMI1SEL_MASK 0xF8 |
| 43 | #define BRDCFG4_EMI1SEL_SHIFT 3 |
| 44 | #define BRDCFG4_EMI2SEL_MASK 0x07 |
| 45 | #define BRDCFG4_EMI2SEL_SHIFT 0 |
| 46 | |
| 47 | /* VID */ |
| 48 | |
| 49 | #define I2C_MUX_CH_VOL_MONITOR 0xA |
| 50 | /* Voltage monitor on channel 2*/ |
| 51 | #define I2C_VOL_MONITOR_ADDR 0x63 |
| 52 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 |
| 53 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 |
| 54 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 |
| 55 | #define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv" |
| 56 | #define CONFIG_VID |
| 57 | |
| 58 | /* The lowest and highest voltage allowed*/ |
| 59 | #define VDD_MV_MIN 775 |
| 60 | #define VDD_MV_MAX 925 |
| 61 | |
| 62 | /* PM Bus commands code for LTC3882*/ |
| 63 | #define PMBUS_CMD_PAGE 0x0 |
| 64 | #define PMBUS_CMD_READ_VOUT 0x8B |
| 65 | #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 |
| 66 | #define PMBUS_CMD_VOUT_COMMAND 0x21 |
| 67 | #define PWM_CHANNEL0 0x0 |
| 68 | |
| 69 | #define CONFIG_VOL_MONITOR_LTC3882_SET |
| 70 | #define CONFIG_VOL_MONITOR_LTC3882_READ |
| 71 | |
| 72 | /* RTC */ |
| 73 | #define CONFIG_SYS_RTC_BUS_NUM 0 |
| 74 | #define I2C_MUX_CH_RTC 0xB |
| 75 | |
| 76 | /* |
| 77 | * MMC |
| 78 | */ |
| 79 | #ifdef CONFIG_MMC |
| 80 | #ifndef __ASSEMBLY__ |
| 81 | u8 qixis_esdhc_detect_quirk(void); |
| 82 | #endif |
| 83 | #define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() |
| 84 | #endif |
| 85 | |
| 86 | /* MAC/PHY configuration */ |
| 87 | #if defined(CONFIG_FSL_MC_ENET) |
| 88 | #define CONFIG_MII |
| 89 | #define CONFIG_ETHPRIME "DPMAC17@rgmii-id" |
| 90 | |
| 91 | #define AQ_PHY_ADDR1 0x00 |
| 92 | #define AQ_PHY_ADDR2 0x01 |
| 93 | #define AQ_PHY_ADDR3 0x02 |
| 94 | #define AQ_PHY_ADDR4 0x03 |
| 95 | |
| 96 | #define CORTINA_NO_FW_UPLOAD |
| 97 | #define CORTINA_PHY_ADDR1 0x0 |
| 98 | |
| 99 | #define INPHI_PHY_ADDR1 0x0 |
| 100 | #define INPHI_PHY_ADDR2 0x1 |
| 101 | |
| 102 | #define RGMII_PHY_ADDR1 0x01 |
| 103 | #define RGMII_PHY_ADDR2 0x02 |
| 104 | |
| 105 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C |
| 106 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1D |
| 107 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E |
| 108 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F |
| 109 | |
| 110 | #endif |
| 111 | |
| 112 | /* EEPROM */ |
| 113 | #define CONFIG_ID_EEPROM |
| 114 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 115 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 116 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 117 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 118 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 119 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
| 120 | |
| 121 | /* Initial environment variables */ |
| 122 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 123 | EXTRA_ENV_SETTINGS \ |
Meenakshi Aggarwal | 69b3894 | 2020-01-10 20:13:19 +0530 | [diff] [blame] | 124 | "boot_scripts=lx2160aqds_boot.scr\0" \ |
| 125 | "boot_script_hdr=hdr_lx2160aqds_bs.out\0" \ |
Pankaj Bansal | 1eba723 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 126 | "BOARD=lx2160aqds\0" \ |
| 127 | "xspi_bootcmd=echo Trying load from flexspi..;" \ |
| 128 | "sf probe 0:0 && sf read $load_addr " \ |
| 129 | "$kernel_start $kernel_size ; env exists secureboot &&" \ |
| 130 | "sf read $kernelheader_addr_r $kernelheader_start " \ |
| 131 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ |
| 132 | " bootm $load_addr#$BOARD\0" \ |
| 133 | "sd_bootcmd=echo Trying load from sd card..;" \ |
| 134 | "mmcinfo; mmc read $load_addr " \ |
| 135 | "$kernel_addr_sd $kernel_size_sd ;" \ |
| 136 | "env exists secureboot && mmc read $kernelheader_addr_r "\ |
| 137 | "$kernelhdr_addr_sd $kernelhdr_size_sd " \ |
| 138 | " && esbc_validate ${kernelheader_addr_r};" \ |
Meenakshi Aggarwal | b7e7a46 | 2020-02-19 23:30:45 +0530 | [diff] [blame] | 139 | "bootm $load_addr#$BOARD\0" \ |
| 140 | "sd2_bootcmd=echo Trying load from emmc card..;" \ |
| 141 | "mmc dev 1; mmcinfo; mmc read $load_addr " \ |
| 142 | "$kernel_addr_sd $kernel_size_sd ;" \ |
| 143 | "env exists secureboot && mmc read $kernelheader_addr_r "\ |
| 144 | "$kernelhdr_addr_sd $kernelhdr_size_sd " \ |
| 145 | " && esbc_validate ${kernelheader_addr_r};" \ |
Pankaj Bansal | 1eba723 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 146 | "bootm $load_addr#$BOARD\0" |
| 147 | |
| 148 | #include <asm/fsl_secure_boot.h> |
| 149 | |
| 150 | #endif /* __LX2_QDS_H */ |