blob: cd79e804a081390aecb4d2abe331bdb421027c37 [file] [log] [blame]
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +00001/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009 Dave Srl www.dave.eu
4 * (C) Copyright 2010 ifm ecomatic GmbH
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +00007 */
8
9#include <common.h>
10#include <asm/bitops.h>
11#include <command.h>
12#include <asm/io.h>
13#include <asm/processor.h>
14#include <asm/mpc512x.h>
15#include <fdt_support.h>
16#ifdef CONFIG_MISC_INIT_R
17#include <i2c.h>
18#endif
19
Gerhard Sittig527a1c72013-06-05 14:51:07 +020020static int mac_diag;
21static int gpio_diag;
22
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +000023DECLARE_GLOBAL_DATA_PTR;
24
25static void gpio_configure(void)
26{
27 immap_t *im;
28 gpio512x_t *gpioregs;
29
30 im = (immap_t *) CONFIG_SYS_IMMR;
31 gpioregs = &im->gpio;
32 out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
33 out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
34
35 /*
36 * out_be32(&gpioregs->gpdir, 0xC2293020);
Gerhard Sittigb5992e72013-06-05 14:51:06 +020037 * workaround for a hardware effect: configure direction in pieces,
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +000038 * setting all outputs at once drops the reset line too low and
39 * makes us lose the MII connection (breaks ethernet for us)
40 */
41 out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
42 setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
43 udelay(10);
44 setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
45 udelay(10);
46 setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
47 udelay(10);
48 setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
49
50 /* to turn from red to yellow when U-Boot runs */
51 setbits_be32(&gpioregs->gpdat, 0x00002020);
52 out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
53 out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
54 out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
55 out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
56}
57
58/* the physical location of the pins */
59#define GPIOKEY_ROW_BITMASK 0x40000000
60#define GPIOKEY_ROW_UPPER 0
61#define GPIOKEY_ROW_LOWER 1
62
63#define GPIOKEY_COL0_BITMASK 0x20000000
64#define GPIOKEY_COL1_BITMASK 0x10000000
65#define GPIOKEY_COL2_BITMASK 0x08000000
66
67/* the logical presentation of pressed keys */
68#define GPIOKEY_BIT_FNLEFT (1 << 5)
69#define GPIOKEY_BIT_FNRIGHT (1 << 4)
70#define GPIOKEY_BIT_DIRUP (1 << 3)
71#define GPIOKEY_BIT_DIRLEFT (1 << 2)
72#define GPIOKEY_BIT_DIRRIGHT (1 << 1)
73#define GPIOKEY_BIT_DIRDOWN (1 << 0)
74
75/* the hotkey combination which starts recovery */
76#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
77 GPIOKEY_BIT_DIRDOWN)
78
79static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
80{
81
82 if (row)
83 setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
84 else
85 clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
86 udelay(10);
87}
88
89static u32 gpio_querykbd(void)
90{
91 immap_t *im;
92 gpio512x_t *gpioregs;
93 u32 keybits;
94 u32 input;
95
96 im = (immap_t *)CONFIG_SYS_IMMR;
97 gpioregs = &im->gpio;
98 keybits = 0;
99
100 /* query upper row */
101 gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
102 input = in_be32(&gpioregs->gpdat);
103 if ((input & GPIOKEY_COL0_BITMASK) == 0)
104 keybits |= GPIOKEY_BIT_FNLEFT;
105 if ((input & GPIOKEY_COL1_BITMASK) == 0)
106 keybits |= GPIOKEY_BIT_DIRUP;
107 if ((input & GPIOKEY_COL2_BITMASK) == 0)
108 keybits |= GPIOKEY_BIT_FNRIGHT;
109
110 /* query lower row */
111 gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
112 input = in_be32(&gpioregs->gpdat);
113 if ((input & GPIOKEY_COL0_BITMASK) == 0)
114 keybits |= GPIOKEY_BIT_DIRLEFT;
115 if ((input & GPIOKEY_COL1_BITMASK) == 0)
116 keybits |= GPIOKEY_BIT_DIRRIGHT;
117 if ((input & GPIOKEY_COL2_BITMASK) == 0)
118 keybits |= GPIOKEY_BIT_DIRDOWN;
119
120 /* return bit pattern for keys */
121 return keybits;
122}
123
124/* excerpt from the recovery's hw_info.h */
125
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000126struct __attribute__ ((__packed__)) eeprom_layout {
127 char magic[3]; /** 'ifm' */
128 u8 len[2]; /** content length without magic/len fields */
129 u8 version[3]; /** structure version */
130 u8 type; /** type of PCB */
131 u8 reserved[0x37]; /** padding up to offset 0x40 */
132 u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */
133};
134
135#define HW_COMP_MAINCPU 2
136
137static struct eeprom_layout eeprom_content;
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000138static int eeprom_is_valid;
139static int eeprom_version;
140
141#define get_eeprom_field_int(name) ({ \
142 int value; \
143 int idx; \
144 value = 0; \
145 for (idx = 0; idx < sizeof(name); idx++) { \
146 value <<= 8; \
147 value |= name[idx]; \
148 } \
149 value; \
150})
151
152static int read_eeprom(void)
153{
Simon Glasseb5ba3a2017-05-12 21:09:49 -0600154 return -ENOSYS;
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000155}
156
157int mac_read_from_eeprom(void)
158{
159 const u8 *mac;
Gerhard Sittig186f9c12013-06-05 14:51:05 +0200160 const char *mac_txt;
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000161
162 if (read_eeprom()) {
163 printf("I2C EEPROM read failed.\n");
164 return -1;
165 }
166
167 if (!eeprom_is_valid) {
168 printf("I2C EEPROM content not valid\n");
169 return -1;
170 }
171
172 mac = NULL;
173 switch (eeprom_version) {
174 case 1:
175 case 2:
176 mac = (const u8 *)&eeprom_content.macaddress;
177 break;
178 }
179
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500180 if (mac && is_valid_ethaddr(mac)) {
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000181 eth_setenv_enetaddr("ethaddr", mac);
Gerhard Sittig527a1c72013-06-05 14:51:07 +0200182 if (mac_diag) {
183 mac_txt = getenv("ethaddr");
184 if (mac_txt)
185 printf("DIAG: MAC value [%s]\n", mac_txt);
186 else
187 printf("DIAG: failed to setup MAC env\n");
188 }
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000189 }
190
191 return 0;
192}
193
194/*
195 * BEWARE!
196 * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
197 * which the ADS, Aria or PDM360NG boards are using
198 * (the steps outlined here refer to the Micron datasheet)
199 */
200u32 sdram_init_seq[] = {
201 /* item 6, at least one NOP after CKE went high */
202 CONFIG_SYS_DDRCMD_NOP,
203 CONFIG_SYS_DDRCMD_NOP,
204 CONFIG_SYS_DDRCMD_NOP,
205 CONFIG_SYS_DDRCMD_NOP,
206 CONFIG_SYS_DDRCMD_NOP,
207 CONFIG_SYS_DDRCMD_NOP,
208 CONFIG_SYS_DDRCMD_NOP,
209 CONFIG_SYS_DDRCMD_NOP,
210 CONFIG_SYS_DDRCMD_NOP,
211 CONFIG_SYS_DDRCMD_NOP,
212 /* item 7, precharge all; item 8, tRP (20ns) */
213 CONFIG_SYS_DDRCMD_PCHG_ALL,
214 CONFIG_SYS_DDRCMD_NOP,
215 /* item 9, extended mode register; item 10, tMRD 10ns) */
216 CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
217 CONFIG_SYS_DDRCMD_NOP,
218 /*
219 * item 11, (base) mode register _with_ reset DLL;
220 * item 12, tMRD (10ns)
221 */
222 CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
223 CONFIG_SYS_MICRON_BMODE_PARAM,
224 CONFIG_SYS_DDRCMD_NOP,
225 /* item 13, precharge all; item 14, tRP (20ns) */
226 CONFIG_SYS_DDRCMD_PCHG_ALL,
227 CONFIG_SYS_DDRCMD_NOP,
228 /*
229 * item 15, auto refresh (i.e. refresh with CKE held high);
230 * item 16, tRFC (70ns)
231 */
232 CONFIG_SYS_DDRCMD_RFSH,
233 CONFIG_SYS_DDRCMD_NOP,
234 CONFIG_SYS_DDRCMD_NOP,
235 CONFIG_SYS_DDRCMD_NOP,
236 CONFIG_SYS_DDRCMD_NOP,
237 CONFIG_SYS_DDRCMD_NOP,
238 CONFIG_SYS_DDRCMD_NOP,
239 CONFIG_SYS_DDRCMD_NOP,
240 CONFIG_SYS_DDRCMD_NOP,
241 /*
242 * item 17, auto refresh (i.e. refresh with CKE held high);
243 * item 18, tRFC (70ns)
244 */
245 CONFIG_SYS_DDRCMD_RFSH,
246 CONFIG_SYS_DDRCMD_NOP,
247 CONFIG_SYS_DDRCMD_NOP,
248 CONFIG_SYS_DDRCMD_NOP,
249 CONFIG_SYS_DDRCMD_NOP,
250 CONFIG_SYS_DDRCMD_NOP,
251 CONFIG_SYS_DDRCMD_NOP,
252 CONFIG_SYS_DDRCMD_NOP,
253 CONFIG_SYS_DDRCMD_NOP,
254 /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
255 CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
256 CONFIG_SYS_DDRCMD_NOP,
257 /*
258 * item 21, "actually done", but make sure 200 DRAM clock cycles
259 * have passed after DLL reset before READ requests are issued
260 * (200 cycles at 160MHz -> 1.25 usec)
261 */
262 /* EMPTY, optional, we don't do it */
263};
264
Simon Glassf1683aa2017-04-06 12:47:05 -0600265int dram_init(void)
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000266{
Simon Glass088454c2017-03-31 08:40:25 -0600267 gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
268 ARRAY_SIZE(sdram_init_seq));
269
270 return 0;
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000271}
272
273int misc_init_r(void)
274{
275 u32 keys;
276 char *s;
277 int want_recovery;
278
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000279 /* setup GPIO directions and initial values */
280 gpio_configure();
281
282 /*
Gerhard Sittigb5992e72013-06-05 14:51:06 +0200283 * enforce the start of the recovery system when
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000284 * - the appropriate keys were pressed
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000285 * - "some" external software told us to
Gerhard Sittig14d4c5f2013-06-05 14:51:08 +0200286 * - a previous installation was aborted or has failed
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000287 */
288 want_recovery = 0;
289 keys = gpio_querykbd();
Gerhard Sittig527a1c72013-06-05 14:51:07 +0200290 if (gpio_diag)
291 printf("GPIO keyboard status [0x%02X]\n", keys);
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000292 if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
Gerhard Sittig527a1c72013-06-05 14:51:07 +0200293 printf("detected recovery request (keyboard)\n");
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000294 want_recovery = 1;
295 }
Gerhard Sittig14d4c5f2013-06-05 14:51:08 +0200296 s = getenv("want_recovery");
297 if ((s != NULL) && (*s != '\0')) {
298 printf("detected recovery request (environment)\n");
299 want_recovery = 1;
300 }
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000301 s = getenv("install_in_progress");
302 if ((s != NULL) && (*s != '\0')) {
Gerhard Sittig527a1c72013-06-05 14:51:07 +0200303 printf("previous installation has not completed\n");
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000304 want_recovery = 1;
305 }
306 s = getenv("install_failed");
307 if ((s != NULL) && (*s != '\0')) {
Gerhard Sittig527a1c72013-06-05 14:51:07 +0200308 printf("previous installation has failed\n");
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000309 want_recovery = 1;
310 }
Gerhard Sittig527a1c72013-06-05 14:51:07 +0200311 if (want_recovery) {
312 printf("enforced start of the recovery system\n");
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000313 setenv("bootcmd", "run recovery");
Gerhard Sittig527a1c72013-06-05 14:51:07 +0200314 }
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000315
316 /*
317 * boot the recovery system without waiting; boot the
318 * production system without waiting by default, only
319 * insert a pause (to provide a chance to get a prompt)
320 * when GPIO keys were pressed during power on
321 */
322 if (want_recovery)
323 setenv("bootdelay", "0");
324 else if (!keys)
325 setenv("bootdelay", "0");
326 else
327 setenv("bootdelay", "2");
328
329 /* get the ethernet MAC from I2C EEPROM */
330 mac_read_from_eeprom();
331
332 return 0;
333}
334
335/* setup specific IO pad configuration */
336static iopin_t ioregs_init[] = {
337 { /* LPC CS3 */
338 offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
339 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
340 IO_PIN_FMUX(1) | IO_PIN_DS(2),
341 },
342 { /* LPC CS1 */
343 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
344 IO_PIN_OVER_DRVSTR,
345 IO_PIN_DS(2),
346 },
347 { /* LPC CS2 */
348 offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
349 IO_PIN_OVER_DRVSTR,
350 IO_PIN_DS(2),
351 },
352 { /* LPC CS4, CS5 */
353 offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
354 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
355 IO_PIN_FMUX(1) | IO_PIN_DS(2),
356 },
357 { /* SDHC CLK, CMD, D0, D1, D2, D3 */
358 offsetof(struct ioctrl512x, io_control_pata_ior), 6,
359 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
360 IO_PIN_FMUX(1) | IO_PIN_DS(2),
361 },
362 { /* GPIO keyboard */
363 offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
364 IO_PIN_OVER_FMUX,
365 IO_PIN_FMUX(3),
366 },
367 { /* GPIO DN1 PF, LCD power, DN2 PF */
368 offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
369 IO_PIN_OVER_FMUX,
370 IO_PIN_FMUX(3),
371 },
372 { /* GPIO reset AS-i */
373 offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
374 IO_PIN_OVER_FMUX,
375 IO_PIN_FMUX(3),
376 },
377 { /* GPIO reset safety */
378 offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
379 IO_PIN_OVER_FMUX,
380 IO_PIN_FMUX(3),
381 },
382 { /* GPIO reset netX */
383 offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
384 IO_PIN_OVER_FMUX,
385 IO_PIN_FMUX(3),
386 },
387 { /* GPIO ma2 en */
388 offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
389 IO_PIN_OVER_FMUX,
390 IO_PIN_FMUX(3),
391 },
392 { /* GPIO SD CD, SD WP */
393 offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
394 IO_PIN_OVER_FMUX,
395 IO_PIN_FMUX(3),
396 },
397 { /* FEC RX DV */
398 offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
399 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
400 IO_PIN_FMUX(2) | IO_PIN_DS(2),
401 },
402 { /* GPIO AS-i prog, AS-i done, LCD backlight */
403 offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
404 IO_PIN_OVER_FMUX,
405 IO_PIN_FMUX(3),
406 },
407 { /* GPIO AS-i wdg */
408 offsetof(struct ioctrl512x, io_control_pci_req2), 1,
409 IO_PIN_OVER_FMUX,
410 IO_PIN_FMUX(3),
411 },
412 { /* GPIO safety wdg */
413 offsetof(struct ioctrl512x, io_control_pci_req1), 1,
414 IO_PIN_OVER_FMUX,
415 IO_PIN_FMUX(3),
416 },
417 { /* GPIO netX wdg */
418 offsetof(struct ioctrl512x, io_control_pci_req0), 1,
419 IO_PIN_OVER_FMUX,
420 IO_PIN_FMUX(3),
421 },
422 { /* GPIO IRQ powerfail */
423 offsetof(struct ioctrl512x, io_control_pci_inta), 1,
424 IO_PIN_OVER_FMUX,
425 IO_PIN_FMUX(3),
426 },
427 { /* GPIO AS-i PWRD */
428 offsetof(struct ioctrl512x, io_control_pci_frame), 1,
429 IO_PIN_OVER_FMUX,
430 IO_PIN_FMUX(3),
431 },
432 { /* GPIO LED0, LED1 */
433 offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
434 IO_PIN_OVER_FMUX,
435 IO_PIN_FMUX(3),
436 },
437 { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
438 offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
439 IO_PIN_OVER_FMUX,
440 IO_PIN_FMUX(3),
441 },
442 { /* DIU clk */
443 offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
444 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
445 IO_PIN_FMUX(2) | IO_PIN_DS(2),
446 },
447 { /* FEC TX ER, CRS */
448 offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
449 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
450 IO_PIN_FMUX(1) | IO_PIN_DS(2),
451 },
452 { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
453 offsetof(struct ioctrl512x, io_control_irq0), 1,
454 IO_PIN_OVER_FMUX,
455 IO_PIN_FMUX(3),
456 },
457 { /*
458 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
459 * rdx 3-0, mdio, rx clk
460 */
461 offsetof(struct ioctrl512x, io_control_psc0_0), 15,
462 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
463 IO_PIN_FMUX(1) | IO_PIN_DS(2),
464 },
465 /* optional: make sure PSC3 remains the serial console */
466 { /* LPC CS6 */
467 offsetof(struct ioctrl512x, io_control_psc3_4), 1,
468 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
469 IO_PIN_FMUX(1) | IO_PIN_DS(2),
470 },
471 /* make sure PSC4 remains available for SPI,
472 *BUT* PSC4_1 is a GPIO kind of SS! */
473 { /* enforce drive strength on the SPI pin */
474 offsetof(struct ioctrl512x, io_control_psc4_0), 5,
475 IO_PIN_OVER_DRVSTR,
476 IO_PIN_DS(2),
477 },
478 {
479 offsetof(struct ioctrl512x, io_control_psc4_1), 1,
480 IO_PIN_OVER_FMUX,
481 IO_PIN_FMUX(3),
482 },
483 /* optional: make sure PSC5 remains available for SPI */
484 { /* enforce drive strength on the SPI pin */
485 offsetof(struct ioctrl512x, io_control_psc5_0), 5,
486 IO_PIN_OVER_DRVSTR,
487 IO_PIN_DS(1),
488 },
489 { /* LPC TSIZ1 */
490 offsetof(struct ioctrl512x, io_control_psc6_0), 1,
491 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
492 IO_PIN_FMUX(1) | IO_PIN_DS(2),
493 },
494 { /* DIU hsync */
495 offsetof(struct ioctrl512x, io_control_psc6_1), 1,
496 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
497 IO_PIN_FMUX(2) | IO_PIN_DS(1),
498 },
499 { /* DIU vsync */
500 offsetof(struct ioctrl512x, io_control_psc6_4), 1,
501 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
502 IO_PIN_FMUX(2) | IO_PIN_DS(1),
503 },
504 { /* PSC7, part of DIU RGB */
505 offsetof(struct ioctrl512x, io_control_psc7_0), 2,
506 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
507 IO_PIN_FMUX(2) | IO_PIN_DS(1),
508 },
509 { /* PSC7, safety UART */
510 offsetof(struct ioctrl512x, io_control_psc7_2), 2,
511 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
512 IO_PIN_FMUX(0) | IO_PIN_DS(1),
513 },
514 { /* DIU (part of) RGB[] */
515 offsetof(struct ioctrl512x, io_control_psc8_3), 16,
516 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
517 IO_PIN_FMUX(2) | IO_PIN_DS(1),
518 },
519 { /* DIU data enable */
520 offsetof(struct ioctrl512x, io_control_psc11_4), 1,
521 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
522 IO_PIN_FMUX(2) | IO_PIN_DS(1),
523 },
524 /* reduce LPB drive strength for improved EMI */
525 { /* LPC OE, LPC RW */
526 offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
527 IO_PIN_OVER_DRVSTR,
528 IO_PIN_DS(2),
529 },
530 { /* LPC AX03 through LPC AD00 */
531 offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
532 IO_PIN_OVER_DRVSTR,
533 IO_PIN_DS(2),
534 },
535 { /* LPC CS5 */
536 offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
537 IO_PIN_OVER_DRVSTR,
538 IO_PIN_DS(2),
539 },
540 { /* SDHC CLK */
541 offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
542 IO_PIN_OVER_DRVSTR,
543 IO_PIN_DS(2),
544 },
545 { /* SDHC DATA */
546 offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
547 IO_PIN_OVER_DRVSTR,
548 IO_PIN_DS(2),
549 },
550};
551
552int checkboard(void)
553{
554 puts("Board: ifm AC14xx\n");
555
556 /* initialize function mux & slew rate IO inter alia on IO Pins */
557 iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
558
559 return 0;
560}
561
Robert P. J. Day7ffe3cd2016-05-19 15:23:12 -0400562#ifdef CONFIG_OF_BOARD_SETUP
Simon Glasse895a4b2014-10-23 18:58:47 -0600563int ft_board_setup(void *blob, bd_t *bd)
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000564{
565 ft_cpu_setup(blob, bd);
Simon Glasse895a4b2014-10-23 18:58:47 -0600566
567 return 0;
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000568}
Robert P. J. Day7ffe3cd2016-05-19 15:23:12 -0400569#endif /* CONFIG_OF_BOARD_SETUP */