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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk507bbe32004-04-18 21:13:41 +00002/*
Michal Simek93768392015-12-01 14:24:20 +01003 * (C) Copyright 2008 - 2015 Michal Simek <monstr@monstr.eu>
Michal Simek53ea9812008-07-11 10:10:31 +02004 * Clean driver and add xilinx constant from header file
wdenk507bbe32004-04-18 21:13:41 +00005 *
Michal Simek53ea9812008-07-11 10:10:31 +02006 * (C) Copyright 2004 Atmark Techno, Inc.
wdenk507bbe32004-04-18 21:13:41 +00007 * Yasushi SHOJI <yashi@atmark-techno.com>
wdenk507bbe32004-04-18 21:13:41 +00008 */
9
10#include <config.h>
Michal Simek49a23e42011-09-25 21:03:08 +000011#include <common.h>
Michal Simek93768392015-12-01 14:24:20 +010012#include <dm.h>
Michal Simek53ea9812008-07-11 10:10:31 +020013#include <asm/io.h>
Michal Simek49a23e42011-09-25 21:03:08 +000014#include <linux/compiler.h>
15#include <serial.h>
wdenk507bbe32004-04-18 21:13:41 +000016
Michal Simek93768392015-12-01 14:24:20 +010017#define SR_TX_FIFO_FULL BIT(3) /* transmit FIFO full */
18#define SR_TX_FIFO_EMPTY BIT(2) /* transmit FIFO empty */
19#define SR_RX_FIFO_VALID_DATA BIT(0) /* data in receive FIFO */
20#define SR_RX_FIFO_FULL BIT(1) /* receive FIFO full */
wdenk507bbe32004-04-18 21:13:41 +000021
Michal Simek8c3bd6b2014-01-21 07:29:47 +010022#define ULITE_CONTROL_RST_TX 0x01
23#define ULITE_CONTROL_RST_RX 0x02
24
Michal Simek49a23e42011-09-25 21:03:08 +000025struct uartlite {
26 unsigned int rx_fifo;
27 unsigned int tx_fifo;
28 unsigned int status;
Michal Simek8c3bd6b2014-01-21 07:29:47 +010029 unsigned int control;
Michal Simek49a23e42011-09-25 21:03:08 +000030};
wdenk507bbe32004-04-18 21:13:41 +000031
Michal Simek93768392015-12-01 14:24:20 +010032struct uartlite_platdata {
33 struct uartlite *regs;
Michal Simek49a23e42011-09-25 21:03:08 +000034};
35
Michal Simek93768392015-12-01 14:24:20 +010036static int uartlite_serial_putc(struct udevice *dev, const char ch)
Michal Simek49a23e42011-09-25 21:03:08 +000037{
Michal Simek93768392015-12-01 14:24:20 +010038 struct uartlite_platdata *plat = dev_get_platdata(dev);
39 struct uartlite *regs = plat->regs;
Michal Simek49a23e42011-09-25 21:03:08 +000040
Michal Simek93768392015-12-01 14:24:20 +010041 if (in_be32(&regs->status) & SR_TX_FIFO_FULL)
42 return -EAGAIN;
Michal Simek49a23e42011-09-25 21:03:08 +000043
Michal Simek93768392015-12-01 14:24:20 +010044 out_be32(&regs->tx_fifo, ch & 0xff);
45
46 return 0;
Michal Simek49a23e42011-09-25 21:03:08 +000047}
48
Michal Simek93768392015-12-01 14:24:20 +010049static int uartlite_serial_getc(struct udevice *dev)
Michal Simek49a23e42011-09-25 21:03:08 +000050{
Michal Simek93768392015-12-01 14:24:20 +010051 struct uartlite_platdata *plat = dev_get_platdata(dev);
52 struct uartlite *regs = plat->regs;
Michal Simek49a23e42011-09-25 21:03:08 +000053
Michal Simek93768392015-12-01 14:24:20 +010054 if (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA))
55 return -EAGAIN;
Michal Simek49a23e42011-09-25 21:03:08 +000056
Michal Simek49a23e42011-09-25 21:03:08 +000057 return in_be32(&regs->rx_fifo) & 0xff;
58}
59
Michal Simek93768392015-12-01 14:24:20 +010060static int uartlite_serial_pending(struct udevice *dev, bool input)
Michal Simek49a23e42011-09-25 21:03:08 +000061{
Michal Simek93768392015-12-01 14:24:20 +010062 struct uartlite_platdata *plat = dev_get_platdata(dev);
63 struct uartlite *regs = plat->regs;
Michal Simek49a23e42011-09-25 21:03:08 +000064
Michal Simek93768392015-12-01 14:24:20 +010065 if (input)
66 return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA;
67
68 return !(in_be32(&regs->status) & SR_TX_FIFO_EMPTY);
Michal Simek49a23e42011-09-25 21:03:08 +000069}
70
Michal Simek93768392015-12-01 14:24:20 +010071static int uartlite_serial_probe(struct udevice *dev)
Michal Simek25239e12012-07-02 10:32:18 +020072{
Michal Simek93768392015-12-01 14:24:20 +010073 struct uartlite_platdata *plat = dev_get_platdata(dev);
74 struct uartlite *regs = plat->regs;
Michal Simek8c3bd6b2014-01-21 07:29:47 +010075
Michal Simek93768392015-12-01 14:24:20 +010076 out_be32(&regs->control, 0);
77 out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
78 in_be32(&regs->control);
Michal Simek8c3bd6b2014-01-21 07:29:47 +010079
Michal Simek93768392015-12-01 14:24:20 +010080 return 0;
Michal Simek25239e12012-07-02 10:32:18 +020081}
82
Michal Simek93768392015-12-01 14:24:20 +010083static int uartlite_serial_ofdata_to_platdata(struct udevice *dev)
Michal Simek49a23e42011-09-25 21:03:08 +000084{
Michal Simek93768392015-12-01 14:24:20 +010085 struct uartlite_platdata *plat = dev_get_platdata(dev);
Michal Simek25239e12012-07-02 10:32:18 +020086
Simon Glassa821c4a2017-05-17 17:18:05 -060087 plat->regs = (struct uartlite *)devfdt_get_addr(dev);
Michal Simek93768392015-12-01 14:24:20 +010088
89 return 0;
Michal Simek49a23e42011-09-25 21:03:08 +000090}
Marek Vasut87d69222012-09-12 19:45:58 +020091
Michal Simek93768392015-12-01 14:24:20 +010092static const struct dm_serial_ops uartlite_serial_ops = {
93 .putc = uartlite_serial_putc,
94 .pending = uartlite_serial_pending,
95 .getc = uartlite_serial_getc,
96};
97
98static const struct udevice_id uartlite_serial_ids[] = {
99 { .compatible = "xlnx,opb-uartlite-1.00.b", },
100 { .compatible = "xlnx,xps-uartlite-1.00.a" },
101 { }
102};
103
104U_BOOT_DRIVER(serial_uartlite) = {
105 .name = "serial_uartlite",
106 .id = UCLASS_SERIAL,
107 .of_match = uartlite_serial_ids,
108 .ofdata_to_platdata = uartlite_serial_ofdata_to_platdata,
109 .platdata_auto_alloc_size = sizeof(struct uartlite_platdata),
110 .probe = uartlite_serial_probe,
111 .ops = &uartlite_serial_ops,
112 .flags = DM_FLAG_PRE_RELOC,
113};
Michal Simek4166ba32015-12-14 16:55:10 +0100114
115#ifdef CONFIG_DEBUG_UART_UARTLITE
116
117#include <debug_uart.h>
118
119static inline void _debug_uart_init(void)
120{
121 struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
122
123 out_be32(&regs->control, 0);
124 out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
125 in_be32(&regs->control);
126}
127
128static inline void _debug_uart_putc(int ch)
129{
130 struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
131
132 while (in_be32(&regs->status) & SR_TX_FIFO_FULL)
133 ;
134
135 out_be32(&regs->tx_fifo, ch & 0xff);
136}
137
138DEBUG_UART_FUNCS
139#endif