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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +09002/*
3 * Configuation settings for the Renesas SH7763RDP board
4 *
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +09007 */
8
9#ifndef __SH7763RDP_H
10#define __SH7763RDP_H
11
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090012#define CONFIG_CPU_SH7763 1
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090013#define __LITTLE_ENDIAN 1
14
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090015#define CONFIG_ENV_OVERWRITE 1
16
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020017#define CONFIG_DISPLAY_BOARDINFO
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090018#undef CONFIG_SHOW_BOOT_PROGRESS
19
20/* SCIF */
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090021#define CONFIG_CONS_SCIF2 1
22
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090025 settings for this board */
26
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090027/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
29#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
30#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
31#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090032
33/* Flash(NOR) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_FLASH_BASE (0xA0000000)
35#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
36#define CONFIG_SYS_MAX_FLASH_BANKS (1)
37#define CONFIG_SYS_MAX_FLASH_SECT (520)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090038
Bin Menga1875592016-02-05 19:30:11 -080039/* U-Boot setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
41#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
42#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090043/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090046
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020048#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#undef CONFIG_SYS_FLASH_QUIET_TEST
50#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090051/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090053/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090055/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090057/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090059/* Use hardware flash sectors protection instead of U-Boot software protection */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#undef CONFIG_SYS_FLASH_PROTECTION
61#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020062#define CONFIG_ENV_SECT_SIZE (128 * 1024)
63#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
65/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
66#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020067#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090069
70/* Clock */
71#define CONFIG_SYS_CLK_FREQ 66666666
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090072#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
73#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020074#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090075
Nobuhiro Iwamatsuba932442008-08-08 16:30:23 +090076/* Ether */
Nobuhiro Iwamatsuba932442008-08-08 16:30:23 +090077#define CONFIG_SH_ETHER_USE_PORT (1)
78#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
Yoshihiro Shimodac8ceca92011-10-31 10:44:18 +090079#define CONFIG_BITBANGMII
80#define CONFIG_BITBANGMII_MULTI
Nobuhiro Iwamatsua80a6612012-05-16 10:23:21 +090081#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Nobuhiro Iwamatsuba932442008-08-08 16:30:23 +090082
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090083#endif /* __SH7763RDP_H */