Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Configuration file for the SAMA5D2 PTC EK Board. |
| 4 | * |
| 5 | * Copyright (C) 2017 Microchip Technology Inc. |
| 6 | * Wenyou Yang <wenyou.yang@microchip.com> |
| 7 | * Ludovic Desroches <ludovic.desroches@microchip.com> |
Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
| 13 | #include "at91-sama5_common.h" |
| 14 | |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 15 | #undef CFG_SYS_AT91_MAIN_CLOCK |
| 16 | #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ |
Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 17 | |
Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 18 | /* SDRAM */ |
Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 19 | #define CFG_SYS_SDRAM_BASE 0x20000000 |
| 20 | #define CFG_SYS_SDRAM_SIZE 0x20000000 |
Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 21 | |
Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 22 | /* NAND Flash */ |
| 23 | #ifdef CONFIG_CMD_NAND |
Tom Rini | 4e59094 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 24 | #define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 |
Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 25 | /* our ALE is AD21 */ |
Tom Rini | 4e59094 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 26 | #define CFG_SYS_NAND_MASK_ALE BIT(21) |
Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 27 | /* our CLE is AD22 */ |
Tom Rini | 4e59094 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 28 | #define CFG_SYS_NAND_MASK_CLE BIT(22) |
Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 29 | #endif |
| 30 | |
| 31 | #endif /* __CONFIG_H */ |