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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +08002/*
3 * Configuration file for the SAMA5D2 PTC EK Board.
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Wenyou Yang <wenyou.yang@microchip.com>
7 * Ludovic Desroches <ludovic.desroches@microchip.com>
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +08008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include "at91-sama5_common.h"
14
Tom Rini65cc0e22022-11-16 13:10:41 -050015#undef CFG_SYS_AT91_MAIN_CLOCK
16#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +080017
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +080018/* SDRAM */
Tom Riniaa6e94d2022-11-16 13:10:37 -050019#define CFG_SYS_SDRAM_BASE 0x20000000
20#define CFG_SYS_SDRAM_SIZE 0x20000000
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +080021
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +080022/* NAND Flash */
23#ifdef CONFIG_CMD_NAND
Tom Rini4e590942022-11-12 17:36:51 -050024#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +080025/* our ALE is AD21 */
Tom Rini4e590942022-11-12 17:36:51 -050026#define CFG_SYS_NAND_MASK_ALE BIT(21)
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +080027/* our CLE is AD22 */
Tom Rini4e590942022-11-12 17:36:51 -050028#define CFG_SYS_NAND_MASK_CLE BIT(22)
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +080029#endif
30
31#endif /* __CONFIG_H */