| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
| Andy Fleming | 61a21e9 | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 2 | * Copyright 2004, 2007 Freescale Semiconductor. |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 3 | * Copyright(c) 2003 Motorola Inc. |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __MPC85xx_H__ |
| 7 | #define __MPC85xx_H__ |
| 8 | |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 9 | #if defined(CONFIG_E500) |
| 10 | #include <e500.h> |
| 11 | #endif |
| 12 | |
| wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 13 | /* |
| 14 | * SCCR - System Clock Control Register, 9-8 |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 15 | */ |
| wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 16 | #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ |
| 17 | #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 18 | #define SCCR_DFBRG_SHIFT 0 |
| 19 | |
| wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 20 | #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ |
| 21 | #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ |
| 22 | #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ |
| 23 | #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 24 | |
| Timur Tabi | e46fedf | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 25 | /* |
| 26 | * Define default values for some CCSR macros to make header files cleaner* |
| 27 | * |
| 28 | * To completely disable CCSR relocation in a board header file, define |
| Tom Rini | 6074a53 | 2022-05-21 11:26:27 -0400 | [diff] [blame] | 29 | * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS |
| Timur Tabi | e46fedf | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 30 | * to a value that is the same as CONFIG_SYS_CCSRBAR. |
| 31 | */ |
| 32 | |
| 33 | #ifdef CONFIG_SYS_CCSRBAR_PHYS |
| 34 | #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ |
| 35 | CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." |
| 36 | #endif |
| 37 | |
| Tom Rini | 6074a53 | 2022-05-21 11:26:27 -0400 | [diff] [blame] | 38 | #if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE) |
| Timur Tabi | e46fedf | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 39 | #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH |
| 40 | #undef CONFIG_SYS_CCSRBAR_PHYS_LOW |
| 41 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 |
| 42 | #endif |
| 43 | |
| 44 | #ifndef CONFIG_SYS_CCSRBAR |
| Wolfgang Denk | 0cf207e | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 45 | #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT |
| Timur Tabi | e46fedf | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 46 | #endif |
| 47 | |
| 48 | #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH |
| 49 | #ifdef CONFIG_PHYS_64BIT |
| 50 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf |
| 51 | #else |
| 52 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 |
| 53 | #endif |
| 54 | #endif |
| 55 | |
| 56 | #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW |
| Wolfgang Denk | 0cf207e | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 57 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT |
| Timur Tabi | e46fedf | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 58 | #endif |
| 59 | |
| 60 | #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ |
| 61 | CONFIG_SYS_CCSRBAR_PHYS_LOW) |
| 62 | |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 63 | #endif /* __MPC85xx_H__ */ |