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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc6097192002-11-03 00:24:07 +00002/*
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkc6097192002-11-03 00:24:07 +00008 */
9
10#ifndef _PCI_H
11#define _PCI_H
12
Minghuan Lianed5b5802015-07-10 11:35:08 +080013#define PCI_CFG_SPACE_SIZE 256
14#define PCI_CFG_SPACE_EXP_SIZE 4096
15
wdenkc6097192002-11-03 00:24:07 +000016/*
17 * Under PCI, each device has 256 bytes of configuration address space,
18 * of which the first 64 bytes are standardized as follows:
19 */
Bin Mengdac01fd2018-08-03 01:14:52 -070020#define PCI_STD_HEADER_SIZEOF 64
wdenkc6097192002-11-03 00:24:07 +000021#define PCI_VENDOR_ID 0x00 /* 16 bits */
22#define PCI_DEVICE_ID 0x02 /* 16 bits */
23#define PCI_COMMAND 0x04 /* 16 bits */
24#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
25#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
26#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
27#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
28#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
29#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
30#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
31#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
32#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
33#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
34
35#define PCI_STATUS 0x06 /* 16 bits */
36#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
37#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
38#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
39#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
40#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
41#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
42#define PCI_STATUS_DEVSEL_FAST 0x000
43#define PCI_STATUS_DEVSEL_MEDIUM 0x200
44#define PCI_STATUS_DEVSEL_SLOW 0x400
45#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
46#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
47#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
48#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
49#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
50
51#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
52 revision */
53#define PCI_REVISION_ID 0x08 /* Revision ID */
54#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
55#define PCI_CLASS_DEVICE 0x0a /* Device class */
56#define PCI_CLASS_CODE 0x0b /* Device class code */
Bill Richardson55ae10f2012-10-20 11:44:34 +000057#define PCI_CLASS_CODE_TOO_OLD 0x00
58#define PCI_CLASS_CODE_STORAGE 0x01
59#define PCI_CLASS_CODE_NETWORK 0x02
60#define PCI_CLASS_CODE_DISPLAY 0x03
61#define PCI_CLASS_CODE_MULTIMEDIA 0x04
62#define PCI_CLASS_CODE_MEMORY 0x05
63#define PCI_CLASS_CODE_BRIDGE 0x06
64#define PCI_CLASS_CODE_COMM 0x07
65#define PCI_CLASS_CODE_PERIPHERAL 0x08
66#define PCI_CLASS_CODE_INPUT 0x09
67#define PCI_CLASS_CODE_DOCKING 0x0A
68#define PCI_CLASS_CODE_PROCESSOR 0x0B
69#define PCI_CLASS_CODE_SERIAL 0x0C
70#define PCI_CLASS_CODE_WIRELESS 0x0D
71#define PCI_CLASS_CODE_I2O 0x0E
72#define PCI_CLASS_CODE_SATELLITE 0x0F
73#define PCI_CLASS_CODE_CRYPTO 0x10
74#define PCI_CLASS_CODE_DATA 0x11
75/* Base Class 0x12 - 0xFE is reserved */
76#define PCI_CLASS_CODE_OTHER 0xFF
77
wdenkc6097192002-11-03 00:24:07 +000078#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
Bill Richardson55ae10f2012-10-20 11:44:34 +000079#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
80#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
81#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
82#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
83#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
84#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
85#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
86#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
87#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
88#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
89#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
90#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
91#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
92#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
93#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
94#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
95#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
96#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
97#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
98#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
99#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
100#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
101#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
102#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
103#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
104#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
105#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
106#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
107#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
108#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
109#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
110#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
111#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
112#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
113#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
114#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
115#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
116#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
117#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
118#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
119#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
120#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
121#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
122#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
123#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
124#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
125#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
126#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
127#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
128#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
129#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
130#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
131#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
132#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
133#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
134#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
135#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
136#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
137#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
138#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
139#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
140#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
141#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
142#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
143#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
144#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
145#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
146#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
147#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
148#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
149#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
150#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
151#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
152#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
153#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
154#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
155#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
156#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
157#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
158#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
159#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
160#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
161#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
162#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
163#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
164#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
165#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
166#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
167#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
168#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
169#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
170#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
171#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
172#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
173#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
174#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
175#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
176#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
177#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
178#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
179#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
180#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
wdenkc6097192002-11-03 00:24:07 +0000181
182#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
183#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
184#define PCI_HEADER_TYPE 0x0e /* 8 bits */
185#define PCI_HEADER_TYPE_NORMAL 0
186#define PCI_HEADER_TYPE_BRIDGE 1
187#define PCI_HEADER_TYPE_CARDBUS 2
188
189#define PCI_BIST 0x0f /* 8 bits */
190#define PCI_BIST_CODE_MASK 0x0f /* Return result */
191#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
192#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
193
194/*
195 * Base addresses specify locations in memory or I/O space.
196 * Decoded size can be determined by writing a value of
197 * 0xffffffff to the register, and reading it back. Only
198 * 1 bits are decoded.
199 */
200#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
201#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
202#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
203#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
204#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
205#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
206#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
207#define PCI_BASE_ADDRESS_SPACE_IO 0x01
208#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
209#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
210#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
211#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
212#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
213#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
Kumar Gala30e76d52008-10-21 08:36:08 -0500214#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
215#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
wdenkc6097192002-11-03 00:24:07 +0000216/* bit 1 is reserved if address_space = 1 */
217
218/* Header type 0 (normal devices) */
219#define PCI_CARDBUS_CIS 0x28
220#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
221#define PCI_SUBSYSTEM_ID 0x2e
222#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
223#define PCI_ROM_ADDRESS_ENABLE 0x01
Kumar Gala30e76d52008-10-21 08:36:08 -0500224#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
wdenkc6097192002-11-03 00:24:07 +0000225
226#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
227
228/* 0x35-0x3b are reserved */
229#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
230#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
231#define PCI_MIN_GNT 0x3e /* 8 bits */
232#define PCI_MAX_LAT 0x3f /* 8 bits */
233
Simon Glass5f48d792015-07-27 15:47:17 -0600234#define PCI_INTERRUPT_LINE_DISABLE 0xff
235
wdenkc6097192002-11-03 00:24:07 +0000236/* Header type 1 (PCI-to-PCI bridges) */
237#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
238#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
239#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
240#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
241#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
242#define PCI_IO_LIMIT 0x1d
243#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
244#define PCI_IO_RANGE_TYPE_16 0x00
245#define PCI_IO_RANGE_TYPE_32 0x01
246#define PCI_IO_RANGE_MASK ~0x0f
247#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
248#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
249#define PCI_MEMORY_LIMIT 0x22
250#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
251#define PCI_MEMORY_RANGE_MASK ~0x0f
252#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
253#define PCI_PREF_MEMORY_LIMIT 0x26
254#define PCI_PREF_RANGE_TYPE_MASK 0x0f
255#define PCI_PREF_RANGE_TYPE_32 0x00
256#define PCI_PREF_RANGE_TYPE_64 0x01
257#define PCI_PREF_RANGE_MASK ~0x0f
258#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
259#define PCI_PREF_LIMIT_UPPER32 0x2c
260#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
261#define PCI_IO_LIMIT_UPPER16 0x32
262/* 0x34 same as for htype 0 */
263/* 0x35-0x3b is reserved */
264#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
265/* 0x3c-0x3d are same as for htype 0 */
266#define PCI_BRIDGE_CONTROL 0x3e
267#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
268#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
269#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
270#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
271#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
272#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
273#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
274
275/* Header type 2 (CardBus bridges) */
276#define PCI_CB_CAPABILITY_LIST 0x14
277/* 0x15 reserved */
278#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
279#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
280#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
281#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
282#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
283#define PCI_CB_MEMORY_BASE_0 0x1c
284#define PCI_CB_MEMORY_LIMIT_0 0x20
285#define PCI_CB_MEMORY_BASE_1 0x24
286#define PCI_CB_MEMORY_LIMIT_1 0x28
287#define PCI_CB_IO_BASE_0 0x2c
288#define PCI_CB_IO_BASE_0_HI 0x2e
289#define PCI_CB_IO_LIMIT_0 0x30
290#define PCI_CB_IO_LIMIT_0_HI 0x32
291#define PCI_CB_IO_BASE_1 0x34
292#define PCI_CB_IO_BASE_1_HI 0x36
293#define PCI_CB_IO_LIMIT_1 0x38
294#define PCI_CB_IO_LIMIT_1_HI 0x3a
295#define PCI_CB_IO_RANGE_MASK ~0x03
296/* 0x3c-0x3d are same as for htype 0 */
297#define PCI_CB_BRIDGE_CONTROL 0x3e
298#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
299#define PCI_CB_BRIDGE_CTL_SERR 0x02
300#define PCI_CB_BRIDGE_CTL_ISA 0x04
301#define PCI_CB_BRIDGE_CTL_VGA 0x08
302#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
303#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
304#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
305#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
306#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
307#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
308#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
309#define PCI_CB_SUBSYSTEM_ID 0x42
310#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
311/* 0x48-0x7f reserved */
312
313/* Capability lists */
314
315#define PCI_CAP_LIST_ID 0 /* Capability ID */
316#define PCI_CAP_ID_PM 0x01 /* Power Management */
317#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
318#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
319#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
320#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
321#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
Bin Meng5d544f92018-08-03 01:14:51 -0700322#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
323#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
324#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
325#define PCI_CAP_ID_DBG 0x0A /* Debug port */
326#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
327#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
328#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
329#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
330#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
331#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
332#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
333#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
334#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
335#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
336#define PCI_CAP_ID_MAX PCI_CAP_ID_EA
wdenkc6097192002-11-03 00:24:07 +0000337#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
338#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
339#define PCI_CAP_SIZEOF 4
340
341/* Power Management Registers */
342
343#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
344#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
345#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
346#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
347#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
348#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
349#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
350#define PCI_PM_CTRL 4 /* PM control and status register */
351#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
352#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
353#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
354#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
355#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
356#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
357#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
358#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
359#define PCI_PM_DATA_REGISTER 7 /* (??) */
360#define PCI_PM_SIZEOF 8
361
362/* AGP registers */
363
364#define PCI_AGP_VERSION 2 /* BCD version number */
365#define PCI_AGP_RFU 3 /* Rest of capability flags */
366#define PCI_AGP_STATUS 4 /* Status register */
367#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
368#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
369#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
370#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
371#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
372#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
373#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
374#define PCI_AGP_COMMAND 8 /* Control register */
375#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
376#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
377#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
378#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
379#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
380#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
381#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
382#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
383#define PCI_AGP_SIZEOF 12
384
Matthew McClintockf0e6f572006-06-28 10:44:49 -0500385/* PCI-X registers */
386
387#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
388#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
389#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
390#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
391#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
392
393
wdenkc6097192002-11-03 00:24:07 +0000394/* Slot Identification */
395
396#define PCI_SID_ESR 2 /* Expansion Slot Register */
397#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
398#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
399#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
400
401/* Message Signalled Interrupts registers */
402
403#define PCI_MSI_FLAGS 2 /* Various flags */
404#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
405#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
406#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
407#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
Ramon Fried8781d042019-04-06 05:12:01 +0300408#define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
wdenkc6097192002-11-03 00:24:07 +0000409#define PCI_MSI_RFU 3 /* Rest of capability flags */
410#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
411#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
412#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
413#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
414
415#define PCI_MAX_PCI_DEVICES 32
416#define PCI_MAX_PCI_FUNCTIONS 8
417
Zhao Qiang287df012013-10-12 13:46:33 +0800418#define PCI_FIND_CAP_TTL 0x48
419#define CAP_START_POS 0x40
420
Minghuan Lianed5b5802015-07-10 11:35:08 +0800421/* Extended Capabilities (PCI-X 2.0 and Express) */
422#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
423#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
424#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
425
426#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
427#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
428#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
429#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
430#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
431#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
432#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
433#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
434#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
435#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
436#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
437#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
438#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
439#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
440#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
441#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
442#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
443#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
444#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
445#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
446#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
447#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
448#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
449#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
450#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
451#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
452#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
Bin Meng5d544f92018-08-03 01:14:51 -0700453#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
454#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
455#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
456#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
Minghuan Lianed5b5802015-07-10 11:35:08 +0800457
wdenkc6097192002-11-03 00:24:07 +0000458/* Include the ID list */
459
460#include <pci_ids.h>
461
Paul Burtonfa5cec02013-11-08 11:18:47 +0000462#ifndef __ASSEMBLY__
463
Kumar Gala30e76d52008-10-21 08:36:08 -0500464#ifdef CONFIG_SYS_PCI_64BIT
465typedef u64 pci_addr_t;
466typedef u64 pci_size_t;
467#else
468typedef u32 pci_addr_t;
469typedef u32 pci_size_t;
470#endif
wdenkc6097192002-11-03 00:24:07 +0000471
Kumar Gala30e76d52008-10-21 08:36:08 -0500472struct pci_region {
473 pci_addr_t bus_start; /* Start on the bus */
474 phys_addr_t phys_start; /* Start in physical address space */
475 pci_size_t size; /* Size */
476 unsigned long flags; /* Resource flags */
477
478 pci_addr_t bus_lower;
wdenkc6097192002-11-03 00:24:07 +0000479};
480
481#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
482#define PCI_REGION_IO 0x00000001 /* PCI IO space */
483#define PCI_REGION_TYPE 0x00000001
Kumar Galaa1790122006-01-11 13:24:15 -0600484#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
wdenkc6097192002-11-03 00:24:07 +0000485
Kumar Galaff4e66e2009-02-06 09:49:31 -0600486#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
wdenkc6097192002-11-03 00:24:07 +0000487#define PCI_REGION_RO 0x00000200 /* Read-only memory */
488
Simon Glassbc3442a2013-06-11 11:14:33 -0700489static inline void pci_set_region(struct pci_region *reg,
Kumar Gala30e76d52008-10-21 08:36:08 -0500490 pci_addr_t bus_start,
Becky Bruce36f32672008-05-07 13:24:57 -0500491 phys_addr_t phys_start,
Kumar Gala30e76d52008-10-21 08:36:08 -0500492 pci_size_t size,
wdenkc6097192002-11-03 00:24:07 +0000493 unsigned long flags) {
494 reg->bus_start = bus_start;
495 reg->phys_start = phys_start;
496 reg->size = size;
497 reg->flags = flags;
498}
499
500typedef int pci_dev_t;
501
Simon Glassff3e0772015-03-05 12:25:25 -0700502#define PCI_BUS(d) (((d) >> 16) & 0xff)
Stefan Roese2253d642019-02-11 08:43:25 +0100503
504/*
505 * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot
506 * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0.
507 * Please see the Linux header include/uapi/linux/pci.h for more details.
508 * This is relevant for the following macros:
509 * PCI_DEV, PCI_FUNC, PCI_DEVFN
510 * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with
511 * the remark from above (input d in bits 15-8 instead of 7-0.
512 */
Simon Glassff3e0772015-03-05 12:25:25 -0700513#define PCI_DEV(d) (((d) >> 11) & 0x1f)
514#define PCI_FUNC(d) (((d) >> 8) & 0x7)
515#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
Stefan Roese2253d642019-02-11 08:43:25 +0100516
Simon Glassff3e0772015-03-05 12:25:25 -0700517#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
518#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
519#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
520#define PCI_VENDEV(v, d) (((v) << 16) | (d))
521#define PCI_ANY_ID (~0)
wdenkc6097192002-11-03 00:24:07 +0000522
523struct pci_device_id {
Simon Glassaba92962015-07-06 16:47:44 -0600524 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
525 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
526 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
527 unsigned long driver_data; /* Data private to the driver */
wdenkc6097192002-11-03 00:24:07 +0000528};
529
530struct pci_controller;
531
532struct pci_config_table {
533 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
534 unsigned int class; /* Class ID, or PCI_ANY_ID */
535 unsigned int bus; /* Bus number, or PCI_ANY_ID */
536 unsigned int dev; /* Device number, or PCI_ANY_ID */
537 unsigned int func; /* Function number, or PCI_ANY_ID */
538
539 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
540 struct pci_config_table *);
541 unsigned long priv[3];
542};
543
Wolfgang Denk993a2272006-03-12 16:54:11 +0100544extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
545 struct pci_config_table *);
wdenkc6097192002-11-03 00:24:07 +0000546extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
547 struct pci_config_table *);
548
Simon Glass62c72992019-05-07 21:41:15 -0600549#define MAX_PCI_REGIONS 7
wdenkc6097192002-11-03 00:24:07 +0000550
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300551#define INDIRECT_TYPE_NO_PCIE_LINK 1
552
wdenkc6097192002-11-03 00:24:07 +0000553/*
554 * Structure of a PCI controller (host bridge)
Simon Glass54fe7b12015-11-26 19:51:21 -0700555 *
556 * With driver model this is dev_get_uclass_priv(bus)
wdenkc6097192002-11-03 00:24:07 +0000557 */
558struct pci_controller {
Simon Glassff3e0772015-03-05 12:25:25 -0700559#ifdef CONFIG_DM_PCI
560 struct udevice *bus;
561 struct udevice *ctlr;
562#else
wdenkc6097192002-11-03 00:24:07 +0000563 struct pci_controller *next;
Simon Glassff3e0772015-03-05 12:25:25 -0700564#endif
wdenkc6097192002-11-03 00:24:07 +0000565
566 int first_busno;
567 int last_busno;
568
569 volatile unsigned int *cfg_addr;
570 volatile unsigned char *cfg_data;
571
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300572 int indirect_type;
573
Simon Glassaec241d2015-06-07 08:50:40 -0600574 /*
575 * TODO(sjg@chromium.org): With driver model we use struct
576 * pci_controller for both the controller and any bridge devices
577 * attached to it. But there is only one region list and it is in the
578 * top-level controller.
579 *
580 * This could be changed so that struct pci_controller is only used
581 * for PCI controllers and a separate UCLASS (or perhaps
582 * UCLASS_PCI_GENERIC) is used for bridges.
583 */
wdenkc6097192002-11-03 00:24:07 +0000584 struct pci_region regions[MAX_PCI_REGIONS];
585 int region_count;
586
587 struct pci_config_table *config_table;
588
589 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
Simon Glassff3e0772015-03-05 12:25:25 -0700590#ifndef CONFIG_DM_PCI
wdenkc6097192002-11-03 00:24:07 +0000591 /* Low-level architecture-dependent routines */
592 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
593 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
594 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
595 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
596 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
597 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
Simon Glassff3e0772015-03-05 12:25:25 -0700598#endif
wdenkc6097192002-11-03 00:24:07 +0000599
600 /* Used by auto config */
Kumar Galaa1790122006-01-11 13:24:15 -0600601 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000602
Simon Glassff3e0772015-03-05 12:25:25 -0700603#ifndef CONFIG_DM_PCI
wdenkc7de8292002-11-19 11:04:11 +0000604 int current_busno;
Leo Liu10fa8d72011-01-19 19:50:47 +0800605
606 void *priv_data;
Simon Glassff3e0772015-03-05 12:25:25 -0700607#endif
wdenkc6097192002-11-03 00:24:07 +0000608};
609
Simon Glassff3e0772015-03-05 12:25:25 -0700610#ifndef CONFIG_DM_PCI
Simon Glassbc3442a2013-06-11 11:14:33 -0700611static inline void pci_set_ops(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000612 int (*read_byte)(struct pci_controller*,
613 pci_dev_t, int where, u8 *),
614 int (*read_word)(struct pci_controller*,
615 pci_dev_t, int where, u16 *),
616 int (*read_dword)(struct pci_controller*,
617 pci_dev_t, int where, u32 *),
618 int (*write_byte)(struct pci_controller*,
619 pci_dev_t, int where, u8),
620 int (*write_word)(struct pci_controller*,
621 pci_dev_t, int where, u16),
622 int (*write_dword)(struct pci_controller*,
623 pci_dev_t, int where, u32)) {
624 hose->read_byte = read_byte;
625 hose->read_word = read_word;
626 hose->read_dword = read_dword;
627 hose->write_byte = write_byte;
628 hose->write_word = write_word;
629 hose->write_dword = write_dword;
630}
Simon Glassff3e0772015-03-05 12:25:25 -0700631#endif
wdenkc6097192002-11-03 00:24:07 +0000632
Gabor Juhos842033e2013-05-30 07:06:12 +0000633#ifdef CONFIG_PCI_INDIRECT_BRIDGE
wdenkc6097192002-11-03 00:24:07 +0000634extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
Gabor Juhos842033e2013-05-30 07:06:12 +0000635#endif
wdenkc6097192002-11-03 00:24:07 +0000636
Simon Glass7e78b9e2015-11-29 13:18:05 -0700637#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
Becky Bruce36f32672008-05-07 13:24:57 -0500638extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
Kumar Gala30e76d52008-10-21 08:36:08 -0500639 pci_addr_t addr, unsigned long flags);
640extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
641 phys_addr_t addr, unsigned long flags);
wdenkc6097192002-11-03 00:24:07 +0000642
643#define pci_phys_to_bus(dev, addr, flags) \
644 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
645#define pci_bus_to_phys(dev, addr, flags) \
646 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
647
Becky Bruce6e61fae2009-02-03 18:10:50 -0600648#define pci_virt_to_bus(dev, addr, flags) \
649 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
650 (virt_to_phys(addr)), (flags))
651#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
652 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
653 (addr), (flags)), \
654 (len), (map_flags))
655
656#define pci_phys_to_mem(dev, addr) \
657 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
658#define pci_mem_to_phys(dev, addr) \
659 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
660#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
661#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
662
663#define pci_virt_to_mem(dev, addr) \
664 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
665#define pci_mem_to_virt(dev, addr, len, map_flags) \
666 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
667#define pci_virt_to_io(dev, addr) \
668 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
669#define pci_io_to_virt(dev, addr, len, map_flags) \
670 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
wdenkc6097192002-11-03 00:24:07 +0000671
Simon Glassdc5740d2015-08-22 15:58:55 -0600672/* For driver model these are defined in macros in pci_compat.c */
wdenkc6097192002-11-03 00:24:07 +0000673extern int pci_hose_read_config_byte(struct pci_controller *hose,
674 pci_dev_t dev, int where, u8 *val);
675extern int pci_hose_read_config_word(struct pci_controller *hose,
676 pci_dev_t dev, int where, u16 *val);
677extern int pci_hose_read_config_dword(struct pci_controller *hose,
678 pci_dev_t dev, int where, u32 *val);
679extern int pci_hose_write_config_byte(struct pci_controller *hose,
680 pci_dev_t dev, int where, u8 val);
681extern int pci_hose_write_config_word(struct pci_controller *hose,
682 pci_dev_t dev, int where, u16 val);
683extern int pci_hose_write_config_dword(struct pci_controller *hose,
684 pci_dev_t dev, int where, u32 val);
Simon Glass3ba5f742015-11-26 19:51:30 -0700685#endif
wdenkc6097192002-11-03 00:24:07 +0000686
Simon Glassff3e0772015-03-05 12:25:25 -0700687#ifndef CONFIG_DM_PCI
wdenkc6097192002-11-03 00:24:07 +0000688extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
689extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
690extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
691extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
692extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
693extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
Simon Glassff3e0772015-03-05 12:25:25 -0700694#endif
wdenkc6097192002-11-03 00:24:07 +0000695
Simon Glass3ba5f742015-11-26 19:51:30 -0700696void pciauto_region_init(struct pci_region *res);
697void pciauto_region_align(struct pci_region *res, pci_size_t size);
698void pciauto_config_init(struct pci_controller *hose);
Tuomas Tynkkynen5ce9aca2018-05-14 23:50:05 +0300699
700/**
701 * pciauto_region_allocate() - Allocate resources from a PCI resource region
702 *
703 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
704 * false, the result will be guaranteed to fit in 32 bits.
705 *
706 * @res: PCI region to allocate from
707 * @size: Amount of bytes to allocate
708 * @bar: Returns the PCI bus address of the allocated resource
709 * @supports_64bit: Whether to allow allocations above the 32-bit boundary
710 * @return 0 if successful, -1 on failure
711 */
Simon Glass3ba5f742015-11-26 19:51:30 -0700712int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
Tuomas Tynkkynend71975a2018-05-14 19:38:13 +0300713 pci_addr_t *bar, bool supports_64bit);
Simon Glass3ba5f742015-11-26 19:51:30 -0700714
715#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
wdenkc6097192002-11-03 00:24:07 +0000716extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
717 pci_dev_t dev, int where, u8 *val);
718extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
719 pci_dev_t dev, int where, u16 *val);
720extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
721 pci_dev_t dev, int where, u8 val);
722extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
723 pci_dev_t dev, int where, u16 val);
724
Becky Bruce6e61fae2009-02-03 18:10:50 -0600725extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
wdenkc6097192002-11-03 00:24:07 +0000726extern void pci_register_hose(struct pci_controller* hose);
727extern struct pci_controller* pci_bus_to_hose(int bus);
Kumar Gala3a0e3c22010-12-17 05:57:25 -0600728extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
Stuart Yodereeb5b1a2016-03-10 10:52:18 -0600729extern struct pci_controller *pci_get_hose_head(void);
wdenkc6097192002-11-03 00:24:07 +0000730
Thierry Reding4efe52b2014-11-12 18:26:49 -0700731extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000732extern int pci_hose_scan(struct pci_controller *hose);
733extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
734
wdenkc6097192002-11-03 00:24:07 +0000735extern void pciauto_setup_device(struct pci_controller *hose,
736 pci_dev_t dev, int bars_num,
737 struct pci_region *mem,
Kumar Galaa1790122006-01-11 13:24:15 -0600738 struct pci_region *prefetch,
wdenkc6097192002-11-03 00:24:07 +0000739 struct pci_region *io);
Linus Walleija3a70722012-03-25 12:13:15 +0000740extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
741 pci_dev_t dev, int sub_bus);
742extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
743 pci_dev_t dev, int sub_bus);
Linus Walleija3a70722012-03-25 12:13:15 +0000744extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000745
746extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
747extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
Simon Glass250e0392015-01-27 22:13:27 -0700748pci_dev_t pci_find_class(unsigned int find_class, int index);
wdenkc6097192002-11-03 00:24:07 +0000749
Zhao Qiang287df012013-10-12 13:46:33 +0800750extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
751 int cap);
752extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
753 u8 hdr_type);
754extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
755 int cap);
756
Minghuan Lianed5b5802015-07-10 11:35:08 +0800757int pci_find_next_ext_capability(struct pci_controller *hose,
758 pci_dev_t dev, int start, int cap);
759int pci_hose_find_ext_capability(struct pci_controller *hose,
760 pci_dev_t dev, int cap);
761
Tim Harvey09918662014-08-07 22:49:56 -0700762#ifdef CONFIG_PCI_FIXUP_DEV
763extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
764 unsigned short vendor,
765 unsigned short device,
766 unsigned short class);
767#endif
Simon Glass3ba5f742015-11-26 19:51:30 -0700768#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
Tim Harvey09918662014-08-07 22:49:56 -0700769
Peter Tyser983eb9d2010-10-29 17:59:27 -0500770const char * pci_class_str(u8 class);
Anton Vorontsovcc2a8c72009-02-19 18:20:41 +0300771int pci_last_busno(void);
772
Jon Loeliger13a7fcd2006-10-19 11:33:52 -0500773#ifdef CONFIG_MPC85xx
774extern void pci_mpc85xx_init (struct pci_controller *hose);
775#endif
Paul Burtonfa5cec02013-11-08 11:18:47 +0000776
Tim Harvey6ecbe132017-05-12 12:58:41 -0700777#ifdef CONFIG_PCIE_IMX
778extern void imx_pcie_remove(void);
779#endif
780
Simon Glass3ba5f742015-11-26 19:51:30 -0700781#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
Simon Glasse8a552e2014-11-14 18:18:30 -0700782/**
783 * pci_write_bar32() - Write the address of a BAR including control bits
784 *
Simon Glass9d731c82016-01-18 20:19:15 -0700785 * This writes a raw address (with control bits) to a bar. This can be used
786 * with devices which require hard-coded addresses, not part of the normal
787 * PCI enumeration process.
Simon Glasse8a552e2014-11-14 18:18:30 -0700788 *
789 * @hose: PCI hose to use
790 * @dev: PCI device to update
791 * @barnum: BAR number (0-5)
792 * @addr: BAR address with control bits
793 */
794void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
Simon Glass9d731c82016-01-18 20:19:15 -0700795 u32 addr);
Simon Glasse8a552e2014-11-14 18:18:30 -0700796
797/**
798 * pci_read_bar32() - read the address of a bar
799 *
800 * @hose: PCI hose to use
801 * @dev: PCI device to inspect
802 * @barnum: BAR number (0-5)
803 * @return address of the bar, masking out any control bits
804 * */
805u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
806
Simon Glass4a2708a2015-01-14 21:37:04 -0700807/**
Simon Glassaab67242015-03-05 12:25:24 -0700808 * pci_hose_find_devices() - Find devices by vendor/device ID
809 *
810 * @hose: PCI hose to search
811 * @busnum: Bus number to search
812 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
813 * @indexp: Pointer to device index to find. To find the first matching
814 * device, pass 0; to find the second, pass 1, etc. This
815 * parameter is decremented for each non-matching device so
816 * can be called repeatedly.
817 */
818pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
819 struct pci_device_id *ids, int *indexp);
Simon Glass3ba5f742015-11-26 19:51:30 -0700820#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
Simon Glassaab67242015-03-05 12:25:24 -0700821
Simon Glassff3e0772015-03-05 12:25:25 -0700822/* Access sizes for PCI reads and writes */
823enum pci_size_t {
824 PCI_SIZE_8,
825 PCI_SIZE_16,
826 PCI_SIZE_32,
827};
828
829struct udevice;
830
831#ifdef CONFIG_DM_PCI
832/**
833 * struct pci_child_platdata - information stored about each PCI device
834 *
835 * Every device on a PCI bus has this per-child data.
836 *
Simon Glass7d38db52019-02-16 20:24:41 -0700837 * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a
Simon Glassff3e0772015-03-05 12:25:25 -0700838 * PCI bus (i.e. UCLASS_PCI)
839 *
840 * @devfn: Encoded device and function index - see PCI_DEVFN()
841 * @vendor: PCI vendor ID (see pci_ids.h)
842 * @device: PCI device ID (see pci_ids.h)
843 * @class: PCI class, 3 bytes: (base, sub, prog-if)
844 */
845struct pci_child_platdata {
846 int devfn;
847 unsigned short vendor;
848 unsigned short device;
849 unsigned int class;
850};
851
852/* PCI bus operations */
853struct dm_pci_ops {
854 /**
855 * read_config() - Read a PCI configuration value
856 *
857 * PCI buses must support reading and writing configuration values
858 * so that the bus can be scanned and its devices configured.
859 *
860 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
861 * If bridges exist it is possible to use the top-level bus to
862 * access a sub-bus. In that case @bus will be the top-level bus
863 * and PCI_BUS(bdf) will be a different (higher) value
864 *
865 * @bus: Bus to read from
866 * @bdf: Bus, device and function to read
867 * @offset: Byte offset within the device's configuration space
868 * @valuep: Place to put the returned value
869 * @size: Access size
870 * @return 0 if OK, -ve on error
871 */
872 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
873 ulong *valuep, enum pci_size_t size);
874 /**
875 * write_config() - Write a PCI configuration value
876 *
877 * @bus: Bus to write to
878 * @bdf: Bus, device and function to write
879 * @offset: Byte offset within the device's configuration space
880 * @value: Value to write
881 * @size: Access size
882 * @return 0 if OK, -ve on error
883 */
884 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
885 ulong value, enum pci_size_t size);
886};
887
888/* Get access to a PCI bus' operations */
889#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
890
891/**
Simon Glass21ccce12015-11-29 13:17:47 -0700892 * dm_pci_get_bdf() - Get the BDF value for a device
Simon Glass4b515e42015-07-06 16:47:46 -0600893 *
894 * @dev: Device to check
895 * @return bus/device/function value (see PCI_BDF())
896 */
Simon Glass21ccce12015-11-29 13:17:47 -0700897pci_dev_t dm_pci_get_bdf(struct udevice *dev);
Simon Glass4b515e42015-07-06 16:47:46 -0600898
899/**
Simon Glassff3e0772015-03-05 12:25:25 -0700900 * pci_bind_bus_devices() - scan a PCI bus and bind devices
901 *
902 * Scan a PCI bus looking for devices. Bind each one that is found. If
903 * devices are already bound that match the scanned devices, just update the
904 * child data so that the device can be used correctly (this happens when
905 * the device tree describes devices we expect to see on the bus).
906 *
907 * Devices that are bound in this way will use a generic PCI driver which
908 * does nothing. The device can still be accessed but will not provide any
909 * driver interface.
910 *
911 * @bus: Bus containing devices to bind
912 * @return 0 if OK, -ve on error
913 */
914int pci_bind_bus_devices(struct udevice *bus);
915
916/**
917 * pci_auto_config_devices() - configure bus devices ready for use
918 *
919 * This works through all devices on a bus by scanning the driver model
920 * data structures (normally these have been set up by pci_bind_bus_devices()
921 * earlier).
922 *
923 * Space is allocated for each PCI base address register (BAR) so that the
924 * devices are mapped into memory and I/O space ready for use.
925 *
926 * @bus: Bus containing devices to bind
927 * @return 0 if OK, -ve on error
928 */
929int pci_auto_config_devices(struct udevice *bus);
930
931/**
Simon Glassf3f1fae2015-11-29 13:17:48 -0700932 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
Simon Glassff3e0772015-03-05 12:25:25 -0700933 *
934 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
935 * @devp: Returns the device for this address, if found
936 * @return 0 if OK, -ENODEV if not found
937 */
Simon Glassf3f1fae2015-11-29 13:17:48 -0700938int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
Simon Glassff3e0772015-03-05 12:25:25 -0700939
940/**
941 * pci_bus_find_devfn() - Find a device on a bus
942 *
943 * @find_devfn: PCI device address (device and function only)
944 * @devp: Returns the device for this address, if found
945 * @return 0 if OK, -ENODEV if not found
946 */
947int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
948 struct udevice **devp);
949
950/**
Simon Glass76c3fbc2015-08-10 07:05:04 -0600951 * pci_find_first_device() - return the first available PCI device
952 *
953 * This function and pci_find_first_device() allow iteration through all
954 * available PCI devices on all buses. Assuming there are any, this will
955 * return the first one.
956 *
957 * @devp: Set to the first available device, or NULL if no more are left
958 * or we got an error
959 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
960 */
961int pci_find_first_device(struct udevice **devp);
962
963/**
964 * pci_find_next_device() - return the next available PCI device
965 *
966 * Finds the next available PCI device after the one supplied, or sets @devp
967 * to NULL if there are no more.
968 *
969 * @devp: On entry, the last device returned. Set to the next available
970 * device, or NULL if no more are left or we got an error
971 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
972 */
973int pci_find_next_device(struct udevice **devp);
974
975/**
Simon Glassff3e0772015-03-05 12:25:25 -0700976 * pci_get_ff() - Returns a mask for the given access size
977 *
978 * @size: Access size
979 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
980 * PCI_SIZE_32
981 */
982int pci_get_ff(enum pci_size_t size);
983
984/**
985 * pci_bus_find_devices () - Find devices on a bus
986 *
987 * @bus: Bus to search
988 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
989 * @indexp: Pointer to device index to find. To find the first matching
990 * device, pass 0; to find the second, pass 1, etc. This
991 * parameter is decremented for each non-matching device so
992 * can be called repeatedly.
993 * @devp: Returns matching device if found
994 * @return 0 if found, -ENODEV if not
995 */
996int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
997 int *indexp, struct udevice **devp);
998
999/**
1000 * pci_find_device_id() - Find a device on any bus
1001 *
1002 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
1003 * @index: Index number of device to find, 0 for the first match, 1 for
1004 * the second, etc.
1005 * @devp: Returns matching device if found
1006 * @return 0 if found, -ENODEV if not
1007 */
1008int pci_find_device_id(struct pci_device_id *ids, int index,
1009 struct udevice **devp);
1010
1011/**
1012 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
1013 *
1014 * This probes the given bus which causes it to be scanned for devices. The
1015 * devices will be bound but not probed.
1016 *
1017 * @hose specifies the PCI hose that will be used for the scan. This is
1018 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
1019 * in @bdf, and is a subordinate bus reachable from @hose.
1020 *
1021 * @hose: PCI hose to scan
1022 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
1023 * @return 0 if OK, -ve on error
1024 */
Simon Glass5e23b8b2015-11-29 13:17:49 -07001025int dm_pci_hose_probe_bus(struct udevice *bus);
Simon Glassff3e0772015-03-05 12:25:25 -07001026
1027/**
1028 * pci_bus_read_config() - Read a configuration value from a device
1029 *
1030 * TODO(sjg@chromium.org): We should be able to pass just a device and have
1031 * it do the right thing. It would be good to have that function also.
1032 *
1033 * @bus: Bus to read from
1034 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
Simon Glass4974a6f2016-03-06 19:27:53 -07001035 * @offset: Register offset to read
Simon Glassff3e0772015-03-05 12:25:25 -07001036 * @valuep: Place to put the returned value
1037 * @size: Access size
1038 * @return 0 if OK, -ve on error
1039 */
1040int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
1041 unsigned long *valuep, enum pci_size_t size);
1042
1043/**
1044 * pci_bus_write_config() - Write a configuration value to a device
1045 *
1046 * @bus: Bus to write from
1047 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
Simon Glass4974a6f2016-03-06 19:27:53 -07001048 * @offset: Register offset to write
Simon Glassff3e0772015-03-05 12:25:25 -07001049 * @value: Value to write
1050 * @size: Access size
1051 * @return 0 if OK, -ve on error
1052 */
1053int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1054 unsigned long value, enum pci_size_t size);
1055
Simon Glass66afb4e2015-08-10 07:05:03 -06001056/**
Simon Glass319dba12016-03-06 19:27:52 -07001057 * pci_bus_clrset_config32() - Update a configuration value for a device
1058 *
1059 * The register at @offset is updated to (oldvalue & ~clr) | set.
1060 *
1061 * @bus: Bus to access
1062 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1063 * @offset: Register offset to update
1064 * @clr: Bits to clear
1065 * @set: Bits to set
1066 * @return 0 if OK, -ve on error
1067 */
1068int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1069 u32 clr, u32 set);
1070
1071/**
Simon Glass66afb4e2015-08-10 07:05:03 -06001072 * Driver model PCI config access functions. Use these in preference to others
1073 * when you have a valid device
1074 */
1075int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
1076 enum pci_size_t size);
1077
1078int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
1079int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
1080int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
1081
1082int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1083 enum pci_size_t size);
1084
1085int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1086int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1087int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1088
Simon Glass319dba12016-03-06 19:27:52 -07001089/**
1090 * These permit convenient read/modify/write on PCI configuration. The
1091 * register is updated to (oldvalue & ~clr) | set.
1092 */
1093int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1094int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1095int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
1096
Simon Glassff3e0772015-03-05 12:25:25 -07001097/*
1098 * The following functions provide access to the above without needing the
1099 * size parameter. We are trying to encourage the use of the 8/16/32-style
1100 * functions, rather than byte/word/dword. But both are supported.
1101 */
1102int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
Bin Meng308143e2016-02-02 05:58:07 -08001103int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1104int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1105int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1106int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1107int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
Simon Glassff3e0772015-03-05 12:25:25 -07001108
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +03001109/**
1110 * pci_generic_mmap_write_config() - Generic helper for writing to
1111 * memory-mapped PCI configuration space.
1112 * @bus: Pointer to the PCI bus
1113 * @addr_f: Callback for calculating the config space address
1114 * @bdf: Identifies the PCI device to access
1115 * @offset: The offset into the device's configuration space
1116 * @value: The value to write
1117 * @size: Indicates the size of access to perform
1118 *
1119 * Write the value @value of size @size from offset @offset within the
1120 * configuration space of the device identified by the bus, device & function
1121 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
1122 * responsible for calculating the CPU address of the respective configuration
1123 * space offset.
1124 *
1125 * Return: 0 on success, else -EINVAL
1126 */
1127int pci_generic_mmap_write_config(
1128 struct udevice *bus,
1129 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1130 pci_dev_t bdf,
1131 uint offset,
1132 ulong value,
1133 enum pci_size_t size);
1134
1135/**
1136 * pci_generic_mmap_read_config() - Generic helper for reading from
1137 * memory-mapped PCI configuration space.
1138 * @bus: Pointer to the PCI bus
1139 * @addr_f: Callback for calculating the config space address
1140 * @bdf: Identifies the PCI device to access
1141 * @offset: The offset into the device's configuration space
1142 * @valuep: A pointer at which to store the read value
1143 * @size: Indicates the size of access to perform
1144 *
1145 * Read a value of size @size from offset @offset within the configuration
1146 * space of the device identified by the bus, device & function numbers in @bdf
1147 * on the PCI bus @bus. The callback function @addr_f is responsible for
1148 * calculating the CPU address of the respective configuration space offset.
1149 *
1150 * Return: 0 on success, else -EINVAL
1151 */
1152int pci_generic_mmap_read_config(
1153 struct udevice *bus,
1154 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1155 pci_dev_t bdf,
1156 uint offset,
1157 ulong *valuep,
1158 enum pci_size_t size);
1159
Simon Glass3ba5f742015-11-26 19:51:30 -07001160#ifdef CONFIG_DM_PCI_COMPAT
Simon Glassff3e0772015-03-05 12:25:25 -07001161/* Compatibility with old naming */
1162static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1163 u32 value)
1164{
1165 return pci_write_config32(pcidev, offset, value);
1166}
1167
Simon Glassff3e0772015-03-05 12:25:25 -07001168/* Compatibility with old naming */
1169static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1170 u16 value)
1171{
1172 return pci_write_config16(pcidev, offset, value);
1173}
1174
Simon Glassff3e0772015-03-05 12:25:25 -07001175/* Compatibility with old naming */
1176static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1177 u8 value)
1178{
1179 return pci_write_config8(pcidev, offset, value);
1180}
1181
Simon Glassff3e0772015-03-05 12:25:25 -07001182/* Compatibility with old naming */
1183static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1184 u32 *valuep)
1185{
1186 return pci_read_config32(pcidev, offset, valuep);
1187}
1188
Simon Glassff3e0772015-03-05 12:25:25 -07001189/* Compatibility with old naming */
1190static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1191 u16 *valuep)
1192{
1193 return pci_read_config16(pcidev, offset, valuep);
1194}
1195
Simon Glassff3e0772015-03-05 12:25:25 -07001196/* Compatibility with old naming */
1197static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1198 u8 *valuep)
1199{
1200 return pci_read_config8(pcidev, offset, valuep);
1201}
Simon Glass3ba5f742015-11-26 19:51:30 -07001202#endif /* CONFIG_DM_PCI_COMPAT */
1203
1204/**
1205 * dm_pciauto_config_device() - configure a device ready for use
1206 *
1207 * Space is allocated for each PCI base address register (BAR) so that the
1208 * devices are mapped into memory and I/O space ready for use.
1209 *
1210 * @dev: Device to configure
1211 * @return 0 if OK, -ve on error
1212 */
1213int dm_pciauto_config_device(struct udevice *dev);
1214
Simon Glass36d0d3b2015-03-05 12:25:28 -07001215/**
Simon Glass9289db62015-11-19 20:26:59 -07001216 * pci_conv_32_to_size() - convert a 32-bit read value to the given size
1217 *
1218 * Some PCI buses must always perform 32-bit reads. The data must then be
1219 * shifted and masked to reflect the required access size and offset. This
1220 * function performs this transformation.
1221 *
1222 * @value: Value to transform (32-bit value read from @offset & ~3)
1223 * @offset: Register offset that was read
1224 * @size: Required size of the result
1225 * @return the value that would have been obtained if the read had been
1226 * performed at the given offset with the correct size
1227 */
1228ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1229
1230/**
1231 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
1232 *
1233 * Some PCI buses must always perform 32-bit writes. To emulate a smaller
1234 * write the old 32-bit data must be read, updated with the required new data
1235 * and written back as a 32-bit value. This function performs the
1236 * transformation from the old value to the new value.
1237 *
1238 * @value: Value to transform (32-bit value read from @offset & ~3)
1239 * @offset: Register offset that should be written
1240 * @size: Required size of the write
1241 * @return the value that should be written as a 32-bit access to @offset & ~3.
1242 */
1243ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1244 enum pci_size_t size);
1245
1246/**
Simon Glass9f60fb02015-11-19 20:27:00 -07001247 * pci_get_controller() - obtain the controller to use for a bus
1248 *
1249 * @dev: Device to check
1250 * @return pointer to the controller device for this bus
1251 */
1252struct udevice *pci_get_controller(struct udevice *dev);
1253
1254/**
Simon Glassf9260332015-11-19 20:27:01 -07001255 * pci_get_regions() - obtain pointers to all the region types
1256 *
1257 * @dev: Device to check
1258 * @iop: Returns a pointer to the I/O region, or NULL if none
1259 * @memp: Returns a pointer to the memory region, or NULL if none
1260 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
1261 * @return the number of non-NULL regions returned, normally 3
1262 */
1263int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1264 struct pci_region **memp, struct pci_region **prefp);
1265
1266/**
Simon Glass9d731c82016-01-18 20:19:15 -07001267 * dm_pci_write_bar32() - Write the address of a BAR
1268 *
1269 * This writes a raw address to a bar
1270 *
1271 * @dev: PCI device to update
1272 * @barnum: BAR number (0-5)
1273 * @addr: BAR address
1274 */
1275void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1276
1277/**
Simon Glassbab17cf2015-11-29 13:17:53 -07001278 * dm_pci_read_bar32() - read a base address register from a device
1279 *
1280 * @dev: Device to check
1281 * @barnum: Bar number to read (numbered from 0)
1282 * @return: value of BAR
1283 */
1284u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
1285
1286/**
Simon Glass21d1fe72015-11-29 13:18:03 -07001287 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
1288 *
1289 * @dev: Device containing the PCI address
1290 * @addr: PCI address to convert
1291 * @flags: Flags for the region type (PCI_REGION_...)
1292 * @return physical address corresponding to that PCI bus address
1293 */
1294phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
1295 unsigned long flags);
1296
1297/**
1298 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
1299 *
1300 * @dev: Device containing the bus address
1301 * @addr: Physical address to convert
1302 * @flags: Flags for the region type (PCI_REGION_...)
1303 * @return PCI bus address corresponding to that physical address
1304 */
1305pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
1306 unsigned long flags);
1307
1308/**
1309 * dm_pci_map_bar() - get a virtual address associated with a BAR region
1310 *
1311 * Looks up a base address register and finds the physical memory address
1312 * that corresponds to it
1313 *
1314 * @dev: Device to check
1315 * @bar: Bar number to read (numbered from 0)
1316 * @flags: Flags for the region type (PCI_REGION_...)
1317 * @return: pointer to the virtual address to use
1318 */
1319void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
1320
Bin Mengdac01fd2018-08-03 01:14:52 -07001321/**
Bin Menga8c5f8d2018-10-15 02:21:21 -07001322 * dm_pci_find_next_capability() - find a capability starting from an offset
1323 *
1324 * Tell if a device supports a given PCI capability. Returns the
1325 * address of the requested capability structure within the device's
1326 * PCI configuration space or 0 in case the device does not support it.
1327 *
1328 * Possible values for @cap:
1329 *
1330 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1331 * %PCI_CAP_ID_PCIX PCI-X
1332 * %PCI_CAP_ID_EXP PCI Express
1333 * %PCI_CAP_ID_MSIX MSI-X
1334 *
1335 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1336 *
1337 * @dev: PCI device to query
1338 * @start: offset to start from
1339 * @cap: capability code
1340 * @return: capability address or 0 if not supported
1341 */
1342int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
1343
1344/**
Bin Mengdac01fd2018-08-03 01:14:52 -07001345 * dm_pci_find_capability() - find a capability
1346 *
1347 * Tell if a device supports a given PCI capability. Returns the
1348 * address of the requested capability structure within the device's
1349 * PCI configuration space or 0 in case the device does not support it.
1350 *
1351 * Possible values for @cap:
1352 *
1353 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1354 * %PCI_CAP_ID_PCIX PCI-X
1355 * %PCI_CAP_ID_EXP PCI Express
1356 * %PCI_CAP_ID_MSIX MSI-X
1357 *
1358 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1359 *
1360 * @dev: PCI device to query
1361 * @cap: capability code
1362 * @return: capability address or 0 if not supported
1363 */
1364int dm_pci_find_capability(struct udevice *dev, int cap);
1365
1366/**
Bin Menga8c5f8d2018-10-15 02:21:21 -07001367 * dm_pci_find_next_ext_capability() - find an extended capability
1368 * starting from an offset
1369 *
1370 * Tell if a device supports a given PCI express extended capability.
1371 * Returns the address of the requested extended capability structure
1372 * within the device's PCI configuration space or 0 in case the device
1373 * does not support it.
1374 *
1375 * Possible values for @cap:
1376 *
1377 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1378 * %PCI_EXT_CAP_ID_VC Virtual Channel
1379 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1380 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1381 *
1382 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1383 *
1384 * @dev: PCI device to query
1385 * @start: offset to start from
1386 * @cap: extended capability code
1387 * @return: extended capability address or 0 if not supported
1388 */
1389int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
1390
1391/**
Bin Mengdac01fd2018-08-03 01:14:52 -07001392 * dm_pci_find_ext_capability() - find an extended capability
1393 *
1394 * Tell if a device supports a given PCI express extended capability.
1395 * Returns the address of the requested extended capability structure
1396 * within the device's PCI configuration space or 0 in case the device
1397 * does not support it.
1398 *
1399 * Possible values for @cap:
1400 *
1401 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1402 * %PCI_EXT_CAP_ID_VC Virtual Channel
1403 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1404 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1405 *
1406 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1407 *
1408 * @dev: PCI device to query
1409 * @cap: extended capability code
1410 * @return: extended capability address or 0 if not supported
1411 */
1412int dm_pci_find_ext_capability(struct udevice *dev, int cap);
1413
Simon Glass21d1fe72015-11-29 13:18:03 -07001414#define dm_pci_virt_to_bus(dev, addr, flags) \
1415 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
1416#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
1417 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
1418 (len), (map_flags))
1419
1420#define dm_pci_phys_to_mem(dev, addr) \
1421 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
1422#define dm_pci_mem_to_phys(dev, addr) \
1423 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
1424#define dm_pci_phys_to_io(dev, addr) \
1425 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
1426#define dm_pci_io_to_phys(dev, addr) \
1427 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
1428
1429#define dm_pci_virt_to_mem(dev, addr) \
1430 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1431#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1432 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
1433#define dm_pci_virt_to_io(dev, addr) \
Simon Glass4974a6f2016-03-06 19:27:53 -07001434 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
Simon Glass21d1fe72015-11-29 13:18:03 -07001435#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
Simon Glass4974a6f2016-03-06 19:27:53 -07001436 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
Simon Glass21d1fe72015-11-29 13:18:03 -07001437
1438/**
Simon Glass5c0bf642015-11-29 13:17:50 -07001439 * dm_pci_find_device() - find a device by vendor/device ID
1440 *
1441 * @vendor: Vendor ID
1442 * @device: Device ID
1443 * @index: 0 to find the first match, 1 for second, etc.
1444 * @devp: Returns pointer to the device, if found
1445 * @return 0 if found, -ve on error
1446 */
1447int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1448 struct udevice **devp);
1449
1450/**
Simon Glassa0eb8352015-11-29 13:17:52 -07001451 * dm_pci_find_class() - find a device by class
1452 *
1453 * @find_class: 3-byte (24-bit) class value to find
1454 * @index: 0 to find the first match, 1 for second, etc.
1455 * @devp: Returns pointer to the device, if found
1456 * @return 0 if found, -ve on error
1457 */
1458int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1459
1460/**
Simon Glass36d0d3b2015-03-05 12:25:28 -07001461 * struct dm_pci_emul_ops - PCI device emulator operations
1462 */
1463struct dm_pci_emul_ops {
1464 /**
1465 * get_devfn(): Check which device and function this emulators
1466 *
1467 * @dev: device to check
1468 * @return the device and function this emulates, or -ve on error
1469 */
1470 int (*get_devfn)(struct udevice *dev);
1471 /**
1472 * read_config() - Read a PCI configuration value
1473 *
1474 * @dev: Emulated device to read from
1475 * @offset: Byte offset within the device's configuration space
1476 * @valuep: Place to put the returned value
1477 * @size: Access size
1478 * @return 0 if OK, -ve on error
1479 */
1480 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
1481 enum pci_size_t size);
1482 /**
1483 * write_config() - Write a PCI configuration value
1484 *
1485 * @dev: Emulated device to write to
1486 * @offset: Byte offset within the device's configuration space
1487 * @value: Value to write
1488 * @size: Access size
1489 * @return 0 if OK, -ve on error
1490 */
1491 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1492 enum pci_size_t size);
1493 /**
1494 * read_io() - Read a PCI I/O value
1495 *
1496 * @dev: Emulated device to read from
1497 * @addr: I/O address to read
1498 * @valuep: Place to put the returned value
1499 * @size: Access size
1500 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1501 * other -ve value on error
1502 */
1503 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1504 enum pci_size_t size);
1505 /**
1506 * write_io() - Write a PCI I/O value
1507 *
1508 * @dev: Emulated device to write from
1509 * @addr: I/O address to write
1510 * @value: Value to write
1511 * @size: Access size
1512 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1513 * other -ve value on error
1514 */
1515 int (*write_io)(struct udevice *dev, unsigned int addr,
1516 ulong value, enum pci_size_t size);
1517 /**
1518 * map_physmem() - Map a device into sandbox memory
1519 *
1520 * @dev: Emulated device to map
1521 * @addr: Memory address, normally corresponding to a PCI BAR.
1522 * The device should have been configured to have a BAR
1523 * at this address.
1524 * @lenp: On entry, the size of the area to map, On exit it is
1525 * updated to the size actually mapped, which may be less
1526 * if the device has less space
1527 * @ptrp: Returns a pointer to the mapped address. The device's
1528 * space can be accessed as @lenp bytes starting here
1529 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1530 * other -ve value on error
1531 */
1532 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1533 unsigned long *lenp, void **ptrp);
1534 /**
1535 * unmap_physmem() - undo a memory mapping
1536 *
1537 * This must be called after map_physmem() to undo the mapping.
1538 * Some devices can use this to check what has been written into
1539 * their mapped memory and perform an operations they require on it.
1540 * In this way, map/unmap can be used as a sort of handshake between
1541 * the emulated device and its users.
1542 *
1543 * @dev: Emuated device to unmap
1544 * @vaddr: Mapped memory address, as passed to map_physmem()
1545 * @len: Size of area mapped, as returned by map_physmem()
1546 * @return 0 if OK, -ve on error
1547 */
1548 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1549 unsigned long len);
1550};
1551
1552/* Get access to a PCI device emulator's operations */
1553#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1554
1555/**
1556 * sandbox_pci_get_emul() - Get the emulation device for a PCI device
1557 *
1558 * Searches for a suitable emulator for the given PCI bus device
1559 *
1560 * @bus: PCI bus to search
1561 * @find_devfn: PCI device and function address (PCI_DEVFN())
Bin Meng43459982018-08-03 01:14:45 -07001562 * @containerp: Returns container device if found
Simon Glass36d0d3b2015-03-05 12:25:28 -07001563 * @emulp: Returns emulated device if found
1564 * @return 0 if found, -ENODEV if not found
1565 */
1566int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
Bin Meng43459982018-08-03 01:14:45 -07001567 struct udevice **containerp, struct udevice **emulp);
Simon Glass36d0d3b2015-03-05 12:25:28 -07001568
Stefan Roeseb5214202019-01-25 11:52:42 +01001569/**
1570 * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device
1571 *
1572 * Get devfn from fdt_pci_addr of the specifified device
1573 *
1574 * @dev: PCI device
1575 * @return devfn in bits 15...8 if found, -ENODEV if not found
1576 */
1577int pci_get_devfn(struct udevice *dev);
1578
Simon Glassaba92962015-07-06 16:47:44 -06001579#endif /* CONFIG_DM_PCI */
1580
1581/**
1582 * PCI_DEVICE - macro used to describe a specific pci device
1583 * @vend: the 16 bit PCI Vendor ID
1584 * @dev: the 16 bit PCI Device ID
1585 *
1586 * This macro is used to create a struct pci_device_id that matches a
1587 * specific device. The subvendor and subdevice fields will be set to
1588 * PCI_ANY_ID.
1589 */
1590#define PCI_DEVICE(vend, dev) \
1591 .vendor = (vend), .device = (dev), \
1592 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1593
1594/**
1595 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
1596 * @vend: the 16 bit PCI Vendor ID
1597 * @dev: the 16 bit PCI Device ID
1598 * @subvend: the 16 bit PCI Subvendor ID
1599 * @subdev: the 16 bit PCI Subdevice ID
1600 *
1601 * This macro is used to create a struct pci_device_id that matches a
1602 * specific device with subsystem information.
1603 */
1604#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1605 .vendor = (vend), .device = (dev), \
1606 .subvendor = (subvend), .subdevice = (subdev)
1607
1608/**
1609 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
1610 * @dev_class: the class, subclass, prog-if triple for this device
1611 * @dev_class_mask: the class mask for this device
1612 *
1613 * This macro is used to create a struct pci_device_id that matches a
1614 * specific PCI class. The vendor, device, subvendor, and subdevice
1615 * fields will be set to PCI_ANY_ID.
1616 */
1617#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1618 .class = (dev_class), .class_mask = (dev_class_mask), \
1619 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1620 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1621
1622/**
1623 * PCI_VDEVICE - macro used to describe a specific pci device in short form
1624 * @vend: the vendor name
1625 * @dev: the 16 bit PCI Device ID
1626 *
1627 * This macro is used to create a struct pci_device_id that matches a
1628 * specific PCI device. The subvendor, and subdevice fields will be set
1629 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1630 * private data.
1631 */
1632
1633#define PCI_VDEVICE(vend, dev) \
1634 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1635 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1636
1637/**
1638 * struct pci_driver_entry - Matches a driver to its pci_device_id list
1639 * @driver: Driver to use
1640 * @match: List of match records for this driver, terminated by {}
1641 */
1642struct pci_driver_entry {
1643 struct driver *driver;
1644 const struct pci_device_id *match;
1645};
1646
1647#define U_BOOT_PCI_DEVICE(__name, __match) \
1648 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1649 .driver = llsym(struct driver, __name, driver), \
1650 .match = __match, \
1651 }
Simon Glassff3e0772015-03-05 12:25:25 -07001652
Paul Burtonfa5cec02013-11-08 11:18:47 +00001653#endif /* __ASSEMBLY__ */
1654#endif /* _PCI_H */