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wdenk0442ed82002-11-03 10:24:00 +00001/*----------------------------------------------------------------------------+
Josh Boyer31773492009-08-07 13:53:20 -04002| This source code is dual-licensed. You may use it under the terms of the
3| GNU General Public License version 2, or under the license below.
wdenk0442ed82002-11-03 10:24:00 +00004|
Wolfgang Denk53677ef2008-05-20 16:00:29 +02005| This source code has been made available to you by IBM on an AS-IS
6| basis. Anyone receiving this source is licensed under IBM
7| copyrights to use it in any way he or she deems fit, including
8| copying it, modifying it, compiling it, and redistributing it either
9| with or without modifications. No license under IBM patents or
10| patent applications is to be implied by the copyright license.
wdenk0442ed82002-11-03 10:24:00 +000011|
Wolfgang Denk53677ef2008-05-20 16:00:29 +020012| Any user of this software should understand that IBM cannot provide
13| technical support for this software and will not be responsible for
14| any consequences resulting from the use of this software.
wdenk0442ed82002-11-03 10:24:00 +000015|
Wolfgang Denk53677ef2008-05-20 16:00:29 +020016| Any person who transfers this source code or any derivative work
17| must include the IBM copyright notice, this paragraph, and the
18| preceding two paragraphs in the transferred software.
wdenk0442ed82002-11-03 10:24:00 +000019|
Wolfgang Denk53677ef2008-05-20 16:00:29 +020020| COPYRIGHT I B M CORPORATION 1999
21| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
wdenk0442ed82002-11-03 10:24:00 +000022+----------------------------------------------------------------------------*/
23
24#ifndef __PPC405_H__
25#define __PPC405_H__
26
Grant Ericksonc821b5f2008-05-22 14:44:14 -070027/* Define bits and masks for real-mode storage attribute control registers */
28#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
29#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
30
Niklaus Gigerdbcc3572009-10-04 20:04:22 +020031#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
Stefan Roese9b94ac62007-10-31 17:55:58 +010032
Stefan Roese5e7abce2010-09-11 09:31:43 +020033/* DCR registers */
34#define PLB0_ACR 0x0087
35
Stefan Roeseafabb492010-09-12 06:21:37 +020036/* SDR registers */
Stefan Roesed1c3b272009-09-09 16:25:29 +020037#define SDR0_PINSTP 0x0040
Stefan Roesedbbd1252007-10-05 17:10:59 +020038
Stefan Roeseafabb492010-09-12 06:21:37 +020039/* CPR registers */
40#define CPR0_CLKUPD 0x0020
41#define CPR0_PLLC 0x0040
42#define CPR0_PLLD 0x0060
43#define CPR0_CPUD 0x0080
44#define CPR0_PLBD 0x00a0
45#define CPR0_OPBD0 0x00c0
46#define CPR0_PERD 0x00e0
Stefan Roesedbbd1252007-10-05 17:10:59 +020047
Stefan Roeseafabb492010-09-12 06:21:37 +020048/*
49 * DMA
50 */
51#define DMA_DCR_BASE 0x0100
52#define DMACR0 (DMA_DCR_BASE + 0x00) /* DMA channel control reg 0 */
53#define DMACT0 (DMA_DCR_BASE + 0x01) /* DMA count reg 0 */
54#define DMADA0 (DMA_DCR_BASE + 0x02) /* DMA destination address reg 0 */
55#define DMASA0 (DMA_DCR_BASE + 0x03) /* DMA source address reg 0 */
56#define DMASB0 (DMA_DCR_BASE + 0x04) /* DMA sg descriptor addr 0 */
57#define DMACR1 (DMA_DCR_BASE + 0x08) /* DMA channel control reg 1 */
58#define DMACT1 (DMA_DCR_BASE + 0x09) /* DMA count reg 1 */
59#define DMADA1 (DMA_DCR_BASE + 0x0a) /* DMA destination address reg 1 */
60#define DMASA1 (DMA_DCR_BASE + 0x0b) /* DMA source address reg 1 */
61#define DMASB1 (DMA_DCR_BASE + 0x0c) /* DMA sg descriptor addr 1 */
62#define DMACR2 (DMA_DCR_BASE + 0x10) /* DMA channel control reg 2 */
63#define DMACT2 (DMA_DCR_BASE + 0x11) /* DMA count reg 2 */
64#define DMADA2 (DMA_DCR_BASE + 0x12) /* DMA destination address reg 2 */
65#define DMASA2 (DMA_DCR_BASE + 0x13) /* DMA source address reg 2 */
66#define DMASB2 (DMA_DCR_BASE + 0x14) /* DMA sg descriptor addr 2 */
67#define DMACR3 (DMA_DCR_BASE + 0x18) /* DMA channel control reg 3 */
68#define DMACT3 (DMA_DCR_BASE + 0x19) /* DMA count reg 3 */
69#define DMADA3 (DMA_DCR_BASE + 0x1a) /* DMA destination address reg 3 */
70#define DMASA3 (DMA_DCR_BASE + 0x1b) /* DMA source address reg 3 */
71#define DMASB3 (DMA_DCR_BASE + 0x1c) /* DMA sg descriptor addr 3 */
72#define DMASR (DMA_DCR_BASE + 0x20) /* DMA status reg */
73#define DMASGC (DMA_DCR_BASE + 0x23) /* DMA scatter/gather command reg*/
74#define DMAADR (DMA_DCR_BASE + 0x24) /* DMA address decode reg */
Stefan Roesedbbd1252007-10-05 17:10:59 +020075
wdenk0442ed82002-11-03 10:24:00 +000076#endif /* __PPC405_H__ */