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Jon Loeligerd9b94f22005-07-25 14:05:07 -05001/*
Kumar Gala8b47d7e2011-01-04 17:57:59 -06002 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
Jon Loeligerd9b94f22005-07-25 14:05:07 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Jon Loeligerd9b94f22005-07-25 14:05:07 -050015 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8548cds board configuration file
25 *
26 * Please refer to doc/README.mpc85xxcds for more info.
27 *
28 */
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* High Level Configuration Options */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
36#define CONFIG_MPC8548 1 /* MPC8548 specific */
37#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
38
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#ifndef CONFIG_SYS_TEXT_BASE
40#define CONFIG_SYS_TEXT_BASE 0xfff80000
41#endif
42
Kumar Gala8b47d7e2011-01-04 17:57:59 -060043#define CONFIG_SYS_SRIO
44#define CONFIG_SRIO1 /* SRIO port 1 */
45
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050046#define CONFIG_PCI /* enable any pci type devices */
47#define CONFIG_PCI1 /* PCI controller 1 */
48#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050049#undef CONFIG_PCI2
50#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala8ff3de62007-12-07 12:17:34 -060051#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050052#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050053
54#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050055#define CONFIG_ENV_OVERWRITE
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050056#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060057#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050058
Jon Loeliger25eedb22008-03-19 15:02:07 -050059#define CONFIG_FSL_VIA
Jon Loeliger25eedb22008-03-19 15:02:07 -050060
Jon Loeligerd9b94f22005-07-25 14:05:07 -050061#ifndef __ASSEMBLY__
62extern unsigned long get_clock_freq(void);
63#endif
64#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
65
66/*
67 * These can be toggled for performance analysis, otherwise use default.
68 */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050069#define CONFIG_L2_CACHE /* toggle L2 cache */
70#define CONFIG_BTB /* toggle branch predition */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050071
72/*
73 * Only possible on E500 Version 2 or newer cores.
74 */
75#define CONFIG_ENABLE_36BIT_PHYS 1
76
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
78#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeligerd9b94f22005-07-25 14:05:07 -050079
80/*
81 * Base addresses -- Note these are effective addresses where the
82 * actual resources get mapped (not physical addresses)
83 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
85#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
86#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
87#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050088
Jon Loeligere31d2c12008-03-18 13:51:06 -050089/* DDR Setup */
90#define CONFIG_FSL_DDR2
91#undef CONFIG_FSL_DDR_INTERACTIVE
92#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
93#define CONFIG_DDR_SPD
Becky Bruce810c4422010-12-17 17:17:58 -060094#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
Jon Loeligere31d2c12008-03-18 13:51:06 -050095
Dave Liu9b0ad1b2008-10-28 17:53:38 +080096#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Jon Loeligere31d2c12008-03-18 13:51:06 -050097#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
98
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
100#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500101
Jon Loeligere31d2c12008-03-18 13:51:06 -0500102#define CONFIG_NUM_DDR_CONTROLLERS 1
103#define CONFIG_DIMM_SLOTS_PER_CTLR 1
104#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500105
Jon Loeligere31d2c12008-03-18 13:51:06 -0500106/* I2C addresses of SPD EEPROMs */
107#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
108
109/* Make sure required options are set */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500110#ifndef CONFIG_SPD_EEPROM
111#error ("CONFIG_SPD_EEPROM is required")
112#endif
113
114#undef CONFIG_CLOCKS_IN_MHZ
115
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500116/*
117 * Local Bus Definitions
118 */
119
120/*
121 * FLASH on the Local Bus
122 * Two banks, 8M each, using the CFI driver.
123 * Boot from BR0/OR0 bank at 0xff00_0000
124 * Alternate BR1/OR1 bank at 0xff80_0000
125 *
126 * BR0, BR1:
127 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
128 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
129 * Port Size = 16 bits = BRx[19:20] = 10
130 * Use GPCM = BRx[24:26] = 000
131 * Valid = BRx[31] = 1
132 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500133 * 0 4 8 12 16 20 24 28
134 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
135 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500136 *
137 * OR0, OR1:
138 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
139 * Reserved ORx[17:18] = 11, confusion here?
140 * CSNT = ORx[20] = 1
141 * ACS = half cycle delay = ORx[21:22] = 11
142 * SCY = 6 = ORx[24:27] = 0110
143 * TRLX = use relaxed timing = ORx[29] = 1
144 * EAD = use external address latch delay = OR[31] = 1
145 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500146 * 0 4 8 12 16 20 24 28
147 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500148 */
149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */
151#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_BR0_PRELIM 0xff801001
154#define CONFIG_SYS_BR1_PRELIM 0xff001001
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_OR0_PRELIM 0xff806e65
157#define CONFIG_SYS_OR1_PRELIM 0xff806e65
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
160#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
161#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
162#undef CONFIG_SYS_FLASH_CHECKSUM
163#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
164#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500165
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200166#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500167
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200168#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_FLASH_CFI
170#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500171
172
173/*
174 * SDRAM on the Local Bus
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
177#define CONFIG_SYS_LBC_CACHE_SIZE 64
178#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
179#define CONFIG_SYS_LBC_NONCACHE_SIZE 64
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */
182#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500183
184/*
185 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500187 *
188 * For BR2, need:
189 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
190 * port-size = 32-bits = BR2[19:20] = 11
191 * no parity checking = BR2[21:22] = 00
192 * SDRAM for MSEL = BR2[24:26] = 011
193 * Valid = BR[31] = 1
194 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500195 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500196 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
197 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500199 * FIXME: the top 17 bits of BR2.
200 */
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_BR2_PRELIM 0xf0001861
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500203
204/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500206 *
207 * For OR2, need:
208 * 64MB mask for AM, OR2[0:7] = 1111 1100
209 * XAM, OR2[17:18] = 11
210 * 9 columns OR2[19-21] = 010
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500211 * 13 rows OR2[23-25] = 100
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500212 * EAD set for extra time OR[31] = 1
213 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500214 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500215 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
216 */
217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_OR2_PRELIM 0xfc006901
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
221#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
222#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
223#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500224
225/*
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500226 * Common settings for all Local Bus SDRAM commands.
227 * At run time, either BSMA1516 (for CPU 1.1)
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500228 * or BSMA1617 (for CPU 1.0) (old)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500229 * is OR'ed in too.
230 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500231#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
232 | LSDMR_PRETOACT7 \
233 | LSDMR_ACTTORW7 \
234 | LSDMR_BL8 \
235 | LSDMR_WRC4 \
236 | LSDMR_CL3 \
237 | LSDMR_RFEN \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500238 )
239
240/*
241 * The CADMUS registers are connected to CS3 on CDS.
242 * The new memory map places CADMUS at 0xf8000000.
243 *
244 * For BR3, need:
245 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
246 * port-size = 8-bits = BR[19:20] = 01
247 * no parity checking = BR[21:22] = 00
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500248 * GPMC for MSEL = BR[24:26] = 000
249 * Valid = BR[31] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500250 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500251 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500252 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
253 *
254 * For OR3, need:
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500255 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500256 * disable buffer ctrl OR[19] = 0
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500257 * CSNT OR[20] = 1
258 * ACS OR[21:22] = 11
259 * XACS OR[23] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500260 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500261 * SETA OR[28] = 0
262 * TRLX OR[29] = 1
263 * EHTR OR[30] = 1
264 * EAD extra time OR[31] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500265 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500266 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500267 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
268 */
269
Jon Loeliger25eedb22008-03-19 15:02:07 -0500270#define CONFIG_FSL_CADMUS
271
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500272#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_BR3_PRELIM 0xf8000801
274#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_INIT_RAM_LOCK 1
277#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200278#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500281
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200282#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500284
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
286#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500287
288/* Serial Port */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500289#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_NS16550
291#define CONFIG_SYS_NS16550_SERIAL
292#define CONFIG_SYS_NS16550_REG_SIZE 1
293#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500294
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500296 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
299#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500300
301/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_HUSH_PARSER
303#ifdef CONFIG_SYS_HUSH_PARSER
304#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500305#endif
306
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500307/* pass open firmware flat tree */
Kumar Galab90d2542007-11-29 00:11:44 -0600308#define CONFIG_OF_LIBFDT 1
309#define CONFIG_OF_BOARD_SETUP 1
310#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500311
Jon Loeliger20476722006-10-20 15:50:15 -0500312/*
313 * I2C
314 */
315#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
316#define CONFIG_HARD_I2C /* I2C with hardware support*/
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500317#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
319#define CONFIG_SYS_I2C_SLAVE 0x7F
320#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
321#define CONFIG_SYS_I2C_OFFSET 0x3000
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500322
Timur Tabie8d18542008-07-18 16:52:23 +0200323/* EEPROM */
324#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_I2C_EEPROM_CCID
326#define CONFIG_SYS_ID_EEPROM
327#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
328#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200329
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500330/*
331 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300332 * Memory space is mapped 1-1, but I/O space must start from 0.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500333 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600334#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500336
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600337#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600338#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600339#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600341#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600342#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
344#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500345
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500346#ifdef CONFIG_PCI2
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600347#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600348#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600349#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600351#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600352#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
354#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500355#endif
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500356
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500357#ifdef CONFIG_PCIE1
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600358#define CONFIG_SYS_PCIE1_NAME "Slot"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600359#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600360#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600361#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600363#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600364#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
366#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500367#endif
Zang Roy-r6191141fb7e02006-12-14 14:14:55 +0800368
369/*
370 * RapidIO MMU
371 */
Kumar Gala8b47d7e2011-01-04 17:57:59 -0600372#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
373#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
374#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
375#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500376
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700377#ifdef CONFIG_LEGACY
378#define BRIDGE_ID 17
379#define VIA_ID 2
380#else
381#define BRIDGE_ID 28
382#define VIA_ID 4
383#endif
384
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500385#if defined(CONFIG_PCI)
386
387#define CONFIG_NET_MULTI
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500388#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500389
390#undef CONFIG_EEPRO100
391#undef CONFIG_TULIP
392
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500393#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500394
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500395#endif /* CONFIG_PCI */
396
397
398#if defined(CONFIG_TSEC_ENET)
399
400#ifndef CONFIG_NET_MULTI
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500401#define CONFIG_NET_MULTI 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500402#endif
403
404#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500405#define CONFIG_TSEC1 1
406#define CONFIG_TSEC1_NAME "eTSEC0"
407#define CONFIG_TSEC2 1
408#define CONFIG_TSEC2_NAME "eTSEC1"
409#define CONFIG_TSEC3 1
410#define CONFIG_TSEC3_NAME "eTSEC2"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500411#define CONFIG_TSEC4
Kim Phillips255a35772007-05-16 16:52:19 -0500412#define CONFIG_TSEC4_NAME "eTSEC3"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500413#undef CONFIG_MPC85XX_FEC
414
415#define TSEC1_PHY_ADDR 0
416#define TSEC2_PHY_ADDR 1
417#define TSEC3_PHY_ADDR 2
418#define TSEC4_PHY_ADDR 3
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500419
420#define TSEC1_PHYIDX 0
421#define TSEC2_PHYIDX 0
422#define TSEC3_PHYIDX 0
423#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500424#define TSEC1_FLAGS TSEC_GIGABIT
425#define TSEC2_FLAGS TSEC_GIGABIT
426#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
427#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500428
429/* Options are: eTSEC[0-3] */
430#define CONFIG_ETHPRIME "eTSEC0"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500431#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500432#endif /* CONFIG_TSEC_ENET */
433
434/*
435 * Environment
436 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200437#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200439#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
440#define CONFIG_ENV_SIZE 0x2000
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500441
442#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500444
Jon Loeliger2835e512007-06-13 13:22:08 -0500445/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500446 * BOOTP options
447 */
448#define CONFIG_BOOTP_BOOTFILESIZE
449#define CONFIG_BOOTP_BOOTPATH
450#define CONFIG_BOOTP_GATEWAY
451#define CONFIG_BOOTP_HOSTNAME
452
453
454/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500455 * Command line configuration.
456 */
457#include <config_cmd_default.h>
458
459#define CONFIG_CMD_PING
460#define CONFIG_CMD_I2C
461#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600462#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500463#define CONFIG_CMD_IRQ
464#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500465#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500466
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500467#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500468 #define CONFIG_CMD_PCI
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500469#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500470
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500471
472#undef CONFIG_WATCHDOG /* watchdog disabled */
473
474/*
475 * Miscellaneous configurable options
476 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500478#define CONFIG_CMDLINE_EDITING /* Command-line editing */
479#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
481#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500482#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500484#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500486#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
488#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
489#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
490#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500491
492/*
493 * For booting Linux, the board info and command line data
Kumar Gala89188a62009-07-15 08:54:50 -0500494 * have to be in the first 16 MB of memory, since this is
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500495 * the maximum mapped by the Linux kernel during initialization.
496 */
Kumar Gala89188a62009-07-15 08:54:50 -0500497#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Kumar Gala7c57f3e2011-01-11 00:52:35 -0600498#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500499
Jon Loeliger2835e512007-06-13 13:22:08 -0500500#if defined(CONFIG_CMD_KGDB)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500501#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
502#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
503#endif
504
505/*
506 * Environment Configuration
507 */
508
509/* The mac addresses for all ethernet interface */
510#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500511#define CONFIG_HAS_ETH0
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500512#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500513#define CONFIG_HAS_ETH1
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500514#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500515#define CONFIG_HAS_ETH2
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500516#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Andy Fleming09f3e092006-09-13 10:34:18 -0500517#define CONFIG_HAS_ETH3
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500518#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500519#endif
520
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500521#define CONFIG_IPADDR 192.168.1.253
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500522
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500523#define CONFIG_HOSTNAME unknown
524#define CONFIG_ROOTPATH /nfsroot
525#define CONFIG_BOOTFILE 8548cds/uImage.uboot
526#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500527
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500528#define CONFIG_SERVERIP 192.168.1.1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500529#define CONFIG_GATEWAYIP 192.168.1.1
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500530#define CONFIG_NETMASK 255.255.255.0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500531
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500532#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500533
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500534#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
535#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500536
537#define CONFIG_BAUDRATE 115200
538
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500539#define CONFIG_EXTRA_ENV_SETTINGS \
540 "netdev=eth0\0" \
541 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
542 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200543 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
544 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
545 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
546 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
547 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500548 "consoledev=ttyS1\0" \
549 "ramdiskaddr=2000000\0" \
Andy Fleming6c543592007-08-13 14:38:06 -0500550 "ramdiskfile=ramdisk.uboot\0" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500551 "fdtaddr=c00000\0" \
Kumar Gala22abb2d2007-11-29 10:34:28 -0600552 "fdtfile=mpc8548cds.dtb\0"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500553
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500554#define CONFIG_NFSBOOTCOMMAND \
555 "setenv bootargs root=/dev/nfs rw " \
556 "nfsroot=$serverip:$rootpath " \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500557 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500558 "console=$consoledev,$baudrate $othbootargs;" \
559 "tftp $loadaddr $bootfile;" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500560 "tftp $fdtaddr $fdtfile;" \
561 "bootm $loadaddr - $fdtaddr"
Andy Fleming8272dc22006-09-13 10:33:35 -0500562
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500563
564#define CONFIG_RAMBOOTCOMMAND \
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500565 "setenv bootargs root=/dev/ram rw " \
566 "console=$consoledev,$baudrate $othbootargs;" \
567 "tftp $ramdiskaddr $ramdiskfile;" \
568 "tftp $loadaddr $bootfile;" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500569 "tftp $fdtaddr $fdtfile;" \
570 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500571
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500572#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500573
574#endif /* __CONFIG_H */