blob: 8cd1fc34c63b5f235ed34cfc25948aa039ee38ae [file] [log] [blame]
wdenk7c202ac2002-09-09 08:35:37 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Alex Zuepke <azu@sysgo.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26
Wolfgang Denkd87080b2006-03-31 18:32:53 +020027DECLARE_GLOBAL_DATA_PTR;
wdenk7c202ac2002-09-09 08:35:37 +000028
29/*
30 * Miscelaneous platform dependent initialisations
31 */
32
33int board_init (void)
34{
wdenk7c202ac2002-09-09 08:35:37 +000035 /* memory and cpu-speed are setup before relocation */
36 /* but if we use InfernoLoader, we must do some inits here */
37
38#ifdef CONFIG_INFERNO
39 {
wdenk8bde7f72003-06-27 21:31:46 +000040 unsigned long temp;
41 __asm__ __volatile__(/* disable MMU, enable icache */
42 "mrc p15, 0, %0, c1, c0\n"
43 "bic %0, %0, #0x00002000\n"
44 "bic %0, %0, #0x0000000f\n"
45 "orr %0, %0, #0x00001000\n"
46 "orr %0, %0, #0x00000002\n"
47 "mcr p15, 0, %0, c1, c0\n"
48 /* flush caches */
49 "mov %0, #0\n"
50 "mcr p15, 0, %0, c7, c7, 0\n"
51 "mcr p15, 0, %0, c8, c7, 0\n"
52 : "=r" (temp)
53 :
54 : "memory");
55 /* setup PCMCIA timing */
56 temp = 0xa0000018;
57 *(unsigned long *)temp = 0x00060006;
wdenk7c202ac2002-09-09 08:35:37 +000058
59 }
wdenk5f535fe2003-09-18 09:21:33 +000060#endif /* CONFIG_INFERNO */
wdenk7c202ac2002-09-09 08:35:37 +000061
62 /* arch number for shannon */
wdenk731215e2004-10-10 18:41:04 +000063 gd->bd->bi_arch_number = MACH_TYPE_SHANNON;
wdenk7c202ac2002-09-09 08:35:37 +000064
65 /* adress of boot parameters */
66 gd->bd->bi_boot_params = 0xc0000100;
67
68 return 0;
69}
70
71int dram_init (void)
72{
73#if defined(PHYS_SDRAM_1) || defined(PHYS_SDRAM_2) || \
74 defined(PHYS_SDRAM_3) || defined(PHYS_SDRAM_4)
wdenk7c202ac2002-09-09 08:35:37 +000075 bd_t *bd = gd->bd;
76#endif
77
78#ifdef PHYS_SDRAM_1
79 bd->bi_dram[0].start = PHYS_SDRAM_1;
80 bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
81#endif
82
83#ifdef PHYS_SDRAM_2
84 bd->bi_dram[1].start = PHYS_SDRAM_2;
85 bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
86#endif
87
88#ifdef PHYS_SDRAM_3
89 bd->bi_dram[2].start = PHYS_SDRAM_3;
90 bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
91#endif
92
93#ifdef PHYS_SDRAM_4
94 bd->bi_dram[3].start = PHYS_SDRAM_4;
95 bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
96#endif
97
98 return (0);
99}