blob: 759686ccd63ec082c66acda7a923548c29509b6d [file] [log] [blame]
Chin Liang Seec5c1af22013-12-30 18:26:14 -06001/*
2 * (C) Copyright 2013 Altera Corporation <www.altera.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Marek Vasutc35ed772015-11-30 20:41:04 +01008#include <asm/arch/clock_manager.h>
Marek Vasutc35ed772015-11-30 20:41:04 +01009#include <asm/arch/system_manager.h>
10#include <dm.h>
Chin Liang Seec5c1af22013-12-30 18:26:14 -060011#include <dwmmc.h>
Pavel Machek498d1a62014-09-08 14:08:45 +020012#include <errno.h>
Marek Vasutc35ed772015-11-30 20:41:04 +010013#include <fdtdec.h>
14#include <libfdt.h>
15#include <linux/err.h>
16#include <malloc.h>
17
18DECLARE_GLOBAL_DATA_PTR;
Chin Liang Seec5c1af22013-12-30 18:26:14 -060019
20static const struct socfpga_clock_manager *clock_manager_base =
21 (void *)SOCFPGA_CLKMGR_ADDRESS;
22static const struct socfpga_system_manager *system_manager_base =
23 (void *)SOCFPGA_SYSMGR_ADDRESS;
24
Simon Glassf1a485a2016-07-05 17:10:16 -060025struct socfpga_dwmci_plat {
26 struct mmc_config cfg;
27 struct mmc mmc;
28};
29
Marek Vasutc35ed772015-11-30 20:41:04 +010030/* socfpga implmentation specific driver private data */
Chin Liang See9a414042015-11-26 09:43:43 +080031struct dwmci_socfpga_priv_data {
Marek Vasutc35ed772015-11-30 20:41:04 +010032 struct dwmci_host host;
33 unsigned int drvsel;
34 unsigned int smplsel;
Chin Liang See9a414042015-11-26 09:43:43 +080035};
36
37static void socfpga_dwmci_clksel(struct dwmci_host *host)
38{
39 struct dwmci_socfpga_priv_data *priv = host->priv;
Dinh Nguyena1684b62015-12-02 13:31:33 -060040 u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
41 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
Chin Liang Seec5c1af22013-12-30 18:26:14 -060042
43 /* Disable SDMMC clock. */
Pavel Machek51fb4552014-07-19 23:57:59 +020044 clrbits_le32(&clock_manager_base->per_pll.en,
Chin Liang Seec5c1af22013-12-30 18:26:14 -060045 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
46
Chin Liang See9a414042015-11-26 09:43:43 +080047 debug("%s: drvsel %d smplsel %d\n", __func__,
48 priv->drvsel, priv->smplsel);
Dinh Nguyena1684b62015-12-02 13:31:33 -060049 writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
Chin Liang Seec5c1af22013-12-30 18:26:14 -060050
51 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
52 readl(&system_manager_base->sdmmcgrp_ctrl));
53
54 /* Enable SDMMC clock */
Pavel Machek51fb4552014-07-19 23:57:59 +020055 setbits_le32(&clock_manager_base->per_pll.en,
Chin Liang Seec5c1af22013-12-30 18:26:14 -060056 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
57}
58
Marek Vasutc35ed772015-11-30 20:41:04 +010059static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
Chin Liang Seec5c1af22013-12-30 18:26:14 -060060{
Marek Vasut129adf52015-07-25 10:48:14 +020061 /* FIXME: probe from DT eventually too/ */
62 const unsigned long clk = cm_get_mmc_controller_clk_hz();
63
Marek Vasutc35ed772015-11-30 20:41:04 +010064 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
65 struct dwmci_host *host = &priv->host;
66 int fifo_depth;
Pavel Machek498d1a62014-09-08 14:08:45 +020067
68 if (clk == 0) {
Marek Vasutc35ed772015-11-30 20:41:04 +010069 printf("DWMMC: MMC clock is zero!");
Pavel Machek498d1a62014-09-08 14:08:45 +020070 return -EINVAL;
71 }
Pavel Machek78606492014-07-21 13:30:19 +020072
Simon Glasse160f7d2017-01-17 16:52:55 -070073 fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutc35ed772015-11-30 20:41:04 +010074 "fifo-depth", 0);
Marek Vasut129adf52015-07-25 10:48:14 +020075 if (fifo_depth < 0) {
Marek Vasutc35ed772015-11-30 20:41:04 +010076 printf("DWMMC: Can't get FIFO depth\n");
Marek Vasut129adf52015-07-25 10:48:14 +020077 return -EINVAL;
78 }
79
Marek Vasutc35ed772015-11-30 20:41:04 +010080 host->name = dev->name;
Simon Glassa821c4a2017-05-17 17:18:05 -060081 host->ioaddr = (void *)devfdt_get_addr(dev);
Simon Glasse160f7d2017-01-17 16:52:55 -070082 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutc35ed772015-11-30 20:41:04 +010083 "bus-width", 4);
Chin Liang Seec5c1af22013-12-30 18:26:14 -060084 host->clksel = socfpga_dwmci_clksel;
Marek Vasutc35ed772015-11-30 20:41:04 +010085
86 /*
87 * TODO(sjg@chromium.org): Remove the need for this hack.
88 * We only have one dwmmc block on gen5 SoCFPGA.
89 */
90 host->dev_index = 0;
Marek Vasut129adf52015-07-25 10:48:14 +020091 /* Fixed clock divide by 4 which due to the SDMMC wrapper */
Pavel Machek498d1a62014-09-08 14:08:45 +020092 host->bus_hz = clk;
Chin Liang Seec5c1af22013-12-30 18:26:14 -060093 host->fifoth_val = MSIZE(0x2) |
Marek Vasut129adf52015-07-25 10:48:14 +020094 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
Simon Glasse160f7d2017-01-17 16:52:55 -070095 priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutc35ed772015-11-30 20:41:04 +010096 "drvsel", 3);
Simon Glasse160f7d2017-01-17 16:52:55 -070097 priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutc35ed772015-11-30 20:41:04 +010098 "smplsel", 0);
Chin Liang See9a414042015-11-26 09:43:43 +080099 host->priv = priv;
Chin Liang Seec5c1af22013-12-30 18:26:14 -0600100
Marek Vasut129adf52015-07-25 10:48:14 +0200101 return 0;
102}
103
Marek Vasutc35ed772015-11-30 20:41:04 +0100104static int socfpga_dwmmc_probe(struct udevice *dev)
Marek Vasut129adf52015-07-25 10:48:14 +0200105{
Simon Glassf1a485a2016-07-05 17:10:16 -0600106#ifdef CONFIG_BLK
107 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
108#endif
Marek Vasutc35ed772015-11-30 20:41:04 +0100109 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
110 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
111 struct dwmci_host *host = &priv->host;
Simon Glassf1a485a2016-07-05 17:10:16 -0600112
113#ifdef CONFIG_BLK
Jaehoon Chunge5113c32016-09-23 19:13:16 +0900114 dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
Simon Glassf1a485a2016-07-05 17:10:16 -0600115 host->mmc = &plat->mmc;
116#else
Marek Vasutc35ed772015-11-30 20:41:04 +0100117 int ret;
Marek Vasut129adf52015-07-25 10:48:14 +0200118
Marek Vasutc35ed772015-11-30 20:41:04 +0100119 ret = add_dwmci(host, host->bus_hz, 400000);
120 if (ret)
121 return ret;
Simon Glassf1a485a2016-07-05 17:10:16 -0600122#endif
123 host->mmc->priv = &priv->host;
Marek Vasutc35ed772015-11-30 20:41:04 +0100124 upriv->mmc = host->mmc;
Simon Glasscffe5d82016-05-01 13:52:34 -0600125 host->mmc->dev = dev;
Marek Vasut129adf52015-07-25 10:48:14 +0200126
Marek Vasutc35ed772015-11-30 20:41:04 +0100127 return 0;
Marek Vasut129adf52015-07-25 10:48:14 +0200128}
Marek Vasutc35ed772015-11-30 20:41:04 +0100129
Simon Glassf1a485a2016-07-05 17:10:16 -0600130static int socfpga_dwmmc_bind(struct udevice *dev)
131{
132#ifdef CONFIG_BLK
133 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
134 int ret;
135
136 ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
137 if (ret)
138 return ret;
139#endif
140
141 return 0;
142}
143
Marek Vasutc35ed772015-11-30 20:41:04 +0100144static const struct udevice_id socfpga_dwmmc_ids[] = {
145 { .compatible = "altr,socfpga-dw-mshc" },
146 { }
147};
148
149U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
150 .name = "socfpga_dwmmc",
151 .id = UCLASS_MMC,
152 .of_match = socfpga_dwmmc_ids,
153 .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
Sylvain Lesnef55ae192016-10-24 18:24:37 +0200154 .ops = &dm_dwmci_ops,
Simon Glassf1a485a2016-07-05 17:10:16 -0600155 .bind = socfpga_dwmmc_bind,
Marek Vasutc35ed772015-11-30 20:41:04 +0100156 .probe = socfpga_dwmmc_probe,
157 .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
Sylvain Lesnef55ae192016-10-24 18:24:37 +0200158 .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
Marek Vasutc35ed772015-11-30 20:41:04 +0100159};