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Tom Warren21ef6a12011-05-31 10:30:37 +00001/*
2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Jaehoon Chung <jh80.chung@samsung.com>
Tom Warren6a474db2016-09-13 10:45:48 -06005 * Portions Copyright 2011-2016 NVIDIA Corporation
Tom Warren21ef6a12011-05-31 10:30:37 +00006 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Tom Warren21ef6a12011-05-31 10:30:37 +00008 */
9
Stephen Warren19815392012-11-06 11:27:30 +000010#include <bouncebuf.h>
Tom Warren21ef6a12011-05-31 10:30:37 +000011#include <common.h>
Simon Glass9d922452017-05-17 17:18:03 -060012#include <dm.h>
Jaehoon Chung915ffa52016-07-19 16:33:36 +090013#include <errno.h>
Simon Glass49cb9302017-07-25 08:30:08 -060014#include <mmc.h>
Stephen Warren98778412011-10-31 06:51:36 +000015#include <asm/gpio.h>
Tom Warren21ef6a12011-05-31 10:30:37 +000016#include <asm/io.h>
Tom Warren150c2492012-09-19 15:50:56 -070017#include <asm/arch-tegra/tegra_mmc.h>
Tom Warren21ef6a12011-05-31 10:30:37 +000018
Tom Warrenc9aa8312013-02-21 12:31:30 +000019DECLARE_GLOBAL_DATA_PTR;
Tom Warren21ef6a12011-05-31 10:30:37 +000020
Simon Glass0e513e72017-04-23 20:02:11 -060021struct tegra_mmc_plat {
22 struct mmc_config cfg;
23 struct mmc mmc;
24};
25
Stephen Warrenf53c4e42016-09-13 10:45:46 -060026struct tegra_mmc_priv {
27 struct tegra_mmc *reg;
Stephen Warrenf53c4e42016-09-13 10:45:46 -060028 struct reset_ctl reset_ctl;
29 struct clk clk;
Stephen Warrenf53c4e42016-09-13 10:45:46 -060030 struct gpio_desc cd_gpio; /* Change Detect GPIO */
31 struct gpio_desc pwr_gpio; /* Power GPIO */
32 struct gpio_desc wp_gpio; /* Write Protect GPIO */
33 unsigned int version; /* SDHCI spec. version */
34 unsigned int clock; /* Current clock (MHz) */
Stephen Warrenf53c4e42016-09-13 10:45:46 -060035};
36
Stephen Warrenf53c4e42016-09-13 10:45:46 -060037static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
38 unsigned short power)
Tom Warren2d348a12013-02-26 12:31:26 -070039{
40 u8 pwr = 0;
41 debug("%s: power = %x\n", __func__, power);
42
43 if (power != (unsigned short)-1) {
44 switch (1 << power) {
45 case MMC_VDD_165_195:
46 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
47 break;
48 case MMC_VDD_29_30:
49 case MMC_VDD_30_31:
50 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
51 break;
52 case MMC_VDD_32_33:
53 case MMC_VDD_33_34:
54 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
55 break;
56 }
57 }
58 debug("%s: pwr = %X\n", __func__, pwr);
59
60 /* Set the bus voltage first (if any) */
Stephen Warrenf53c4e42016-09-13 10:45:46 -060061 writeb(pwr, &priv->reg->pwrcon);
Tom Warren2d348a12013-02-26 12:31:26 -070062 if (pwr == 0)
63 return;
64
65 /* Now enable bus power */
66 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
Stephen Warrenf53c4e42016-09-13 10:45:46 -060067 writeb(pwr, &priv->reg->pwrcon);
Tom Warren2d348a12013-02-26 12:31:26 -070068}
69
Stephen Warrenf53c4e42016-09-13 10:45:46 -060070static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
71 struct mmc_data *data,
72 struct bounce_buffer *bbstate)
Tom Warren21ef6a12011-05-31 10:30:37 +000073{
74 unsigned char ctrl;
75
Tom Warren21ef6a12011-05-31 10:30:37 +000076
Stephen Warren19815392012-11-06 11:27:30 +000077 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
78 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
79 data->blocksize);
80
Stephen Warrenf53c4e42016-09-13 10:45:46 -060081 writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
Tom Warren21ef6a12011-05-31 10:30:37 +000082 /*
83 * DMASEL[4:3]
84 * 00 = Selects SDMA
85 * 01 = Reserved
86 * 10 = Selects 32-bit Address ADMA2
87 * 11 = Selects 64-bit Address ADMA2
88 */
Stephen Warrenf53c4e42016-09-13 10:45:46 -060089 ctrl = readb(&priv->reg->hostctl);
Anton staaf8e42f0d2011-11-10 11:56:49 +000090 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
91 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
Stephen Warrenf53c4e42016-09-13 10:45:46 -060092 writeb(ctrl, &priv->reg->hostctl);
Tom Warren21ef6a12011-05-31 10:30:37 +000093
94 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
Stephen Warrenf53c4e42016-09-13 10:45:46 -060095 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
96 writew(data->blocks, &priv->reg->blkcnt);
Tom Warren21ef6a12011-05-31 10:30:37 +000097}
98
Stephen Warrenf53c4e42016-09-13 10:45:46 -060099static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
100 struct mmc_data *data)
Tom Warren21ef6a12011-05-31 10:30:37 +0000101{
102 unsigned short mode;
103 debug(" mmc_set_transfer_mode called\n");
104 /*
105 * TRNMOD
106 * MUL1SIN0[5] : Multi/Single Block Select
107 * RD1WT0[4] : Data Transfer Direction Select
108 * 1 = read
109 * 0 = write
110 * ENACMD12[2] : Auto CMD12 Enable
111 * ENBLKCNT[1] : Block Count Enable
112 * ENDMA[0] : DMA Enable
113 */
Anton staaf8e42f0d2011-11-10 11:56:49 +0000114 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
115 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
116
Tom Warren21ef6a12011-05-31 10:30:37 +0000117 if (data->blocks > 1)
Anton staaf8e42f0d2011-11-10 11:56:49 +0000118 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
119
Tom Warren21ef6a12011-05-31 10:30:37 +0000120 if (data->flags & MMC_DATA_READ)
Anton staaf8e42f0d2011-11-10 11:56:49 +0000121 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
Tom Warren21ef6a12011-05-31 10:30:37 +0000122
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600123 writew(mode, &priv->reg->trnmod);
Tom Warren21ef6a12011-05-31 10:30:37 +0000124}
125
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600126static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
127 struct mmc_cmd *cmd,
128 struct mmc_data *data,
129 unsigned int timeout)
Tom Warren21ef6a12011-05-31 10:30:37 +0000130{
Tom Warren21ef6a12011-05-31 10:30:37 +0000131 /*
132 * PRNSTS
Anton staaf0963ff32011-11-10 11:56:52 +0000133 * CMDINHDAT[1] : Command Inhibit (DAT)
134 * CMDINHCMD[0] : Command Inhibit (CMD)
Tom Warren21ef6a12011-05-31 10:30:37 +0000135 */
Anton staaf0963ff32011-11-10 11:56:52 +0000136 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
Tom Warren21ef6a12011-05-31 10:30:37 +0000137
138 /*
139 * We shouldn't wait for data inhibit for stop commands, even
140 * though they might use busy signaling
141 */
Anton staaf0963ff32011-11-10 11:56:52 +0000142 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
143 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
Tom Warren21ef6a12011-05-31 10:30:37 +0000144
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600145 while (readl(&priv->reg->prnsts) & mask) {
Tom Warren21ef6a12011-05-31 10:30:37 +0000146 if (timeout == 0) {
147 printf("%s: timeout error\n", __func__);
148 return -1;
149 }
150 timeout--;
151 udelay(1000);
152 }
153
Anton staaf0963ff32011-11-10 11:56:52 +0000154 return 0;
155}
156
Simon Glass0e513e72017-04-23 20:02:11 -0600157static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600158 struct mmc_data *data,
159 struct bounce_buffer *bbstate)
Anton staaf0963ff32011-11-10 11:56:52 +0000160{
Simon Glass0e513e72017-04-23 20:02:11 -0600161 struct tegra_mmc_priv *priv = dev_get_priv(dev);
Anton staaf0963ff32011-11-10 11:56:52 +0000162 int flags, i;
163 int result;
Anatolij Gustschin60e242e2012-03-28 03:40:00 +0000164 unsigned int mask = 0;
Anton staaf0963ff32011-11-10 11:56:52 +0000165 unsigned int retry = 0x100000;
166 debug(" mmc_send_cmd called\n");
167
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600168 result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
Anton staaf0963ff32011-11-10 11:56:52 +0000169
170 if (result < 0)
171 return result;
172
Tom Warren21ef6a12011-05-31 10:30:37 +0000173 if (data)
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600174 tegra_mmc_prepare_data(priv, data, bbstate);
Tom Warren21ef6a12011-05-31 10:30:37 +0000175
176 debug("cmd->arg: %08x\n", cmd->cmdarg);
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600177 writel(cmd->cmdarg, &priv->reg->argument);
Tom Warren21ef6a12011-05-31 10:30:37 +0000178
179 if (data)
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600180 tegra_mmc_set_transfer_mode(priv, data);
Tom Warren21ef6a12011-05-31 10:30:37 +0000181
182 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
183 return -1;
184
185 /*
186 * CMDREG
187 * CMDIDX[13:8] : Command index
188 * DATAPRNT[5] : Data Present Select
189 * ENCMDIDX[4] : Command Index Check Enable
190 * ENCMDCRC[3] : Command CRC Check Enable
191 * RSPTYP[1:0]
192 * 00 = No Response
193 * 01 = Length 136
194 * 10 = Length 48
195 * 11 = Length 48 Check busy after response
196 */
197 if (!(cmd->resp_type & MMC_RSP_PRESENT))
Anton staaf8e42f0d2011-11-10 11:56:49 +0000198 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
Tom Warren21ef6a12011-05-31 10:30:37 +0000199 else if (cmd->resp_type & MMC_RSP_136)
Anton staaf8e42f0d2011-11-10 11:56:49 +0000200 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
Tom Warren21ef6a12011-05-31 10:30:37 +0000201 else if (cmd->resp_type & MMC_RSP_BUSY)
Anton staaf8e42f0d2011-11-10 11:56:49 +0000202 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
Tom Warren21ef6a12011-05-31 10:30:37 +0000203 else
Anton staaf8e42f0d2011-11-10 11:56:49 +0000204 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
Tom Warren21ef6a12011-05-31 10:30:37 +0000205
206 if (cmd->resp_type & MMC_RSP_CRC)
Anton staaf8e42f0d2011-11-10 11:56:49 +0000207 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
Tom Warren21ef6a12011-05-31 10:30:37 +0000208 if (cmd->resp_type & MMC_RSP_OPCODE)
Anton staaf8e42f0d2011-11-10 11:56:49 +0000209 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
Tom Warren21ef6a12011-05-31 10:30:37 +0000210 if (data)
Anton staaf8e42f0d2011-11-10 11:56:49 +0000211 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
Tom Warren21ef6a12011-05-31 10:30:37 +0000212
213 debug("cmd: %d\n", cmd->cmdidx);
214
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600215 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
Tom Warren21ef6a12011-05-31 10:30:37 +0000216
217 for (i = 0; i < retry; i++) {
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600218 mask = readl(&priv->reg->norintsts);
Tom Warren21ef6a12011-05-31 10:30:37 +0000219 /* Command Complete */
Anton staaf8e42f0d2011-11-10 11:56:49 +0000220 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
Tom Warren21ef6a12011-05-31 10:30:37 +0000221 if (!data)
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600222 writel(mask, &priv->reg->norintsts);
Tom Warren21ef6a12011-05-31 10:30:37 +0000223 break;
224 }
225 }
226
227 if (i == retry) {
228 printf("%s: waiting for status update\n", __func__);
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600229 writel(mask, &priv->reg->norintsts);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900230 return -ETIMEDOUT;
Tom Warren21ef6a12011-05-31 10:30:37 +0000231 }
232
Anton staaf8e42f0d2011-11-10 11:56:49 +0000233 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
Tom Warren21ef6a12011-05-31 10:30:37 +0000234 /* Timeout Error */
235 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600236 writel(mask, &priv->reg->norintsts);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900237 return -ETIMEDOUT;
Anton staaf8e42f0d2011-11-10 11:56:49 +0000238 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
Tom Warren21ef6a12011-05-31 10:30:37 +0000239 /* Error Interrupt */
240 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600241 writel(mask, &priv->reg->norintsts);
Tom Warren21ef6a12011-05-31 10:30:37 +0000242 return -1;
243 }
244
245 if (cmd->resp_type & MMC_RSP_PRESENT) {
246 if (cmd->resp_type & MMC_RSP_136) {
247 /* CRC is stripped so we need to do some shifting. */
248 for (i = 0; i < 4; i++) {
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600249 unsigned long offset = (unsigned long)
250 (&priv->reg->rspreg3 - i);
Tom Warren21ef6a12011-05-31 10:30:37 +0000251 cmd->response[i] = readl(offset) << 8;
252
253 if (i != 3) {
254 cmd->response[i] |=
255 readb(offset - 1);
256 }
257 debug("cmd->resp[%d]: %08x\n",
258 i, cmd->response[i]);
259 }
260 } else if (cmd->resp_type & MMC_RSP_BUSY) {
261 for (i = 0; i < retry; i++) {
262 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600263 if (readl(&priv->reg->prnsts)
Tom Warren21ef6a12011-05-31 10:30:37 +0000264 & (1 << 20)) /* DAT[0] */
265 break;
266 }
267
268 if (i == retry) {
269 printf("%s: card is still busy\n", __func__);
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600270 writel(mask, &priv->reg->norintsts);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900271 return -ETIMEDOUT;
Tom Warren21ef6a12011-05-31 10:30:37 +0000272 }
273
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600274 cmd->response[0] = readl(&priv->reg->rspreg0);
Tom Warren21ef6a12011-05-31 10:30:37 +0000275 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
276 } else {
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600277 cmd->response[0] = readl(&priv->reg->rspreg0);
Tom Warren21ef6a12011-05-31 10:30:37 +0000278 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
279 }
280 }
281
282 if (data) {
Anton staaf9b3d1872011-11-10 11:56:51 +0000283 unsigned long start = get_timer(0);
284
Tom Warren21ef6a12011-05-31 10:30:37 +0000285 while (1) {
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600286 mask = readl(&priv->reg->norintsts);
Tom Warren21ef6a12011-05-31 10:30:37 +0000287
Anton staaf8e42f0d2011-11-10 11:56:49 +0000288 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
Tom Warren21ef6a12011-05-31 10:30:37 +0000289 /* Error Interrupt */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600290 writel(mask, &priv->reg->norintsts);
Tom Warren21ef6a12011-05-31 10:30:37 +0000291 printf("%s: error during transfer: 0x%08x\n",
292 __func__, mask);
293 return -1;
Anton staaf8e42f0d2011-11-10 11:56:49 +0000294 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
Anton staaf5a762e22011-11-10 11:56:50 +0000295 /*
296 * DMA Interrupt, restart the transfer where
297 * it was interrupted.
298 */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600299 unsigned int address = readl(&priv->reg->sysad);
Anton staaf5a762e22011-11-10 11:56:50 +0000300
Tom Warren21ef6a12011-05-31 10:30:37 +0000301 debug("DMA end\n");
Anton staaf5a762e22011-11-10 11:56:50 +0000302 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600303 &priv->reg->norintsts);
304 writel(address, &priv->reg->sysad);
Anton staaf8e42f0d2011-11-10 11:56:49 +0000305 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
Tom Warren21ef6a12011-05-31 10:30:37 +0000306 /* Transfer Complete */
307 debug("r/w is done\n");
308 break;
Marcel Ziswiler09fb7362014-10-04 01:48:53 +0200309 } else if (get_timer(start) > 8000UL) {
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600310 writel(mask, &priv->reg->norintsts);
Anton staaf9b3d1872011-11-10 11:56:51 +0000311 printf("%s: MMC Timeout\n"
312 " Interrupt status 0x%08x\n"
313 " Interrupt status enable 0x%08x\n"
314 " Interrupt signal enable 0x%08x\n"
315 " Present status 0x%08x\n",
316 __func__, mask,
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600317 readl(&priv->reg->norintstsen),
318 readl(&priv->reg->norintsigen),
319 readl(&priv->reg->prnsts));
Anton staaf9b3d1872011-11-10 11:56:51 +0000320 return -1;
Tom Warren21ef6a12011-05-31 10:30:37 +0000321 }
322 }
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600323 writel(mask, &priv->reg->norintsts);
Tom Warren21ef6a12011-05-31 10:30:37 +0000324 }
325
326 udelay(1000);
327 return 0;
328}
329
Simon Glass0e513e72017-04-23 20:02:11 -0600330static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600331 struct mmc_data *data)
Stephen Warren19815392012-11-06 11:27:30 +0000332{
333 void *buf;
334 unsigned int bbflags;
335 size_t len;
336 struct bounce_buffer bbstate;
337 int ret;
338
339 if (data) {
340 if (data->flags & MMC_DATA_READ) {
341 buf = data->dest;
342 bbflags = GEN_BB_WRITE;
343 } else {
344 buf = (void *)data->src;
345 bbflags = GEN_BB_READ;
346 }
347 len = data->blocks * data->blocksize;
348
349 bounce_buffer_start(&bbstate, buf, len, bbflags);
350 }
351
Simon Glass0e513e72017-04-23 20:02:11 -0600352 ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
Stephen Warren19815392012-11-06 11:27:30 +0000353
354 if (data)
355 bounce_buffer_stop(&bbstate);
356
357 return ret;
358}
359
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600360static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
Tom Warren21ef6a12011-05-31 10:30:37 +0000361{
Stephen Warrene8adca92016-09-13 10:46:01 -0600362 ulong rate;
Simon Glass4ed59e72011-09-21 12:40:04 +0000363 int div;
Tom Warren21ef6a12011-05-31 10:30:37 +0000364 unsigned short clk;
365 unsigned long timeout;
Simon Glass4ed59e72011-09-21 12:40:04 +0000366
Tom Warren21ef6a12011-05-31 10:30:37 +0000367 debug(" mmc_change_clock called\n");
368
Simon Glass4ed59e72011-09-21 12:40:04 +0000369 /*
Tom Warren2d348a12013-02-26 12:31:26 -0700370 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
Simon Glass4ed59e72011-09-21 12:40:04 +0000371 */
Tom Warren21ef6a12011-05-31 10:30:37 +0000372 if (clock == 0)
373 goto out;
Stephen Warrene8adca92016-09-13 10:46:01 -0600374
375 rate = clk_set_rate(&priv->clk, clock);
376 div = (rate + clock - 1) / clock;
Simon Glass4ed59e72011-09-21 12:40:04 +0000377 debug("div = %d\n", div);
Tom Warren21ef6a12011-05-31 10:30:37 +0000378
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600379 writew(0, &priv->reg->clkcon);
Tom Warren21ef6a12011-05-31 10:30:37 +0000380
Tom Warren21ef6a12011-05-31 10:30:37 +0000381 /*
382 * CLKCON
383 * SELFREQ[15:8] : base clock divided by value
384 * ENSDCLK[2] : SD Clock Enable
385 * STBLINTCLK[1] : Internal Clock Stable
386 * ENINTCLK[0] : Internal Clock Enable
387 */
Simon Glass4ed59e72011-09-21 12:40:04 +0000388 div >>= 1;
Anton staaf8e42f0d2011-11-10 11:56:49 +0000389 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
390 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600391 writew(clk, &priv->reg->clkcon);
Tom Warren21ef6a12011-05-31 10:30:37 +0000392
393 /* Wait max 10 ms */
394 timeout = 10;
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600395 while (!(readw(&priv->reg->clkcon) &
Anton staaf8e42f0d2011-11-10 11:56:49 +0000396 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
Tom Warren21ef6a12011-05-31 10:30:37 +0000397 if (timeout == 0) {
398 printf("%s: timeout error\n", __func__);
399 return;
400 }
401 timeout--;
402 udelay(1000);
403 }
404
Anton staaf8e42f0d2011-11-10 11:56:49 +0000405 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600406 writew(clk, &priv->reg->clkcon);
Tom Warren21ef6a12011-05-31 10:30:37 +0000407
408 debug("mmc_change_clock: clkcon = %08X\n", clk);
Tom Warren21ef6a12011-05-31 10:30:37 +0000409
410out:
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600411 priv->clock = clock;
Tom Warren21ef6a12011-05-31 10:30:37 +0000412}
413
Simon Glass0e513e72017-04-23 20:02:11 -0600414static int tegra_mmc_set_ios(struct udevice *dev)
Tom Warren21ef6a12011-05-31 10:30:37 +0000415{
Simon Glass0e513e72017-04-23 20:02:11 -0600416 struct tegra_mmc_priv *priv = dev_get_priv(dev);
417 struct mmc *mmc = mmc_get_mmc_dev(dev);
Tom Warren21ef6a12011-05-31 10:30:37 +0000418 unsigned char ctrl;
419 debug(" mmc_set_ios called\n");
420
421 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
422
423 /* Change clock first */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600424 tegra_mmc_change_clock(priv, mmc->clock);
Tom Warren21ef6a12011-05-31 10:30:37 +0000425
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600426 ctrl = readb(&priv->reg->hostctl);
Tom Warren21ef6a12011-05-31 10:30:37 +0000427
428 /*
429 * WIDE8[5]
430 * 0 = Depend on WIDE4
431 * 1 = 8-bit mode
432 * WIDE4[1]
433 * 1 = 4-bit mode
434 * 0 = 1-bit mode
435 */
436 if (mmc->bus_width == 8)
437 ctrl |= (1 << 5);
438 else if (mmc->bus_width == 4)
439 ctrl |= (1 << 1);
440 else
Simon Glass542b5f82017-06-07 21:11:48 -0600441 ctrl &= ~(1 << 1 | 1 << 5);
Tom Warren21ef6a12011-05-31 10:30:37 +0000442
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600443 writeb(ctrl, &priv->reg->hostctl);
Tom Warren21ef6a12011-05-31 10:30:37 +0000444 debug("mmc_set_ios: hostctl = %08X\n", ctrl);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900445
446 return 0;
Tom Warren21ef6a12011-05-31 10:30:37 +0000447}
448
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600449static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
Stephen Warren6b835882016-09-13 10:45:44 -0600450{
451#if defined(CONFIG_TEGRA30)
Stephen Warren6b835882016-09-13 10:45:44 -0600452 u32 val;
453
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600454 debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
Stephen Warren6b835882016-09-13 10:45:44 -0600455
456 /* Set the pad drive strength for SDMMC1 or 3 only */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600457 if (priv->reg != (void *)0x78000000 &&
458 priv->reg != (void *)0x78000400) {
Stephen Warren6b835882016-09-13 10:45:44 -0600459 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
460 __func__);
461 return;
462 }
463
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600464 val = readl(&priv->reg->sdmemcmppadctl);
Stephen Warren6b835882016-09-13 10:45:44 -0600465 val &= 0xFFFFFFF0;
466 val |= MEMCOMP_PADCTRL_VREF;
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600467 writel(val, &priv->reg->sdmemcmppadctl);
Stephen Warren6b835882016-09-13 10:45:44 -0600468
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600469 val = readl(&priv->reg->autocalcfg);
Stephen Warren6b835882016-09-13 10:45:44 -0600470 val &= 0xFFFF0000;
471 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600472 writel(val, &priv->reg->autocalcfg);
Stephen Warren6b835882016-09-13 10:45:44 -0600473#endif
474}
475
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600476static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
Tom Warren21ef6a12011-05-31 10:30:37 +0000477{
478 unsigned int timeout;
479 debug(" mmc_reset called\n");
480
481 /*
482 * RSTALL[0] : Software reset for all
483 * 1 = reset
484 * 0 = work
485 */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600486 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
Tom Warren21ef6a12011-05-31 10:30:37 +0000487
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600488 priv->clock = 0;
Tom Warren21ef6a12011-05-31 10:30:37 +0000489
490 /* Wait max 100 ms */
491 timeout = 100;
492
493 /* hw clears the bit when it's done */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600494 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
Tom Warren21ef6a12011-05-31 10:30:37 +0000495 if (timeout == 0) {
496 printf("%s: timeout error\n", __func__);
497 return;
498 }
499 timeout--;
500 udelay(1000);
501 }
Tom Warren2d348a12013-02-26 12:31:26 -0700502
503 /* Set SD bus voltage & enable bus power */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600504 tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
Tom Warren2d348a12013-02-26 12:31:26 -0700505 debug("%s: power control = %02X, host control = %02X\n", __func__,
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600506 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
Tom Warren2d348a12013-02-26 12:31:26 -0700507
508 /* Make sure SDIO pads are set up */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600509 tegra_mmc_pad_init(priv);
Tom Warren21ef6a12011-05-31 10:30:37 +0000510}
511
Simon Glass0e513e72017-04-23 20:02:11 -0600512static int tegra_mmc_init(struct udevice *dev)
Tom Warren21ef6a12011-05-31 10:30:37 +0000513{
Simon Glass0e513e72017-04-23 20:02:11 -0600514 struct tegra_mmc_priv *priv = dev_get_priv(dev);
515 struct mmc *mmc = mmc_get_mmc_dev(dev);
Tom Warren21ef6a12011-05-31 10:30:37 +0000516 unsigned int mask;
Tom Warren6a474db2016-09-13 10:45:48 -0600517 debug(" tegra_mmc_init called\n");
Tom Warren21ef6a12011-05-31 10:30:37 +0000518
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600519 tegra_mmc_reset(priv, mmc);
Tom Warren21ef6a12011-05-31 10:30:37 +0000520
Marcel Ziswiler4119b702017-03-25 01:18:22 +0100521#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
522 /*
523 * Disable the external clock loopback and use the internal one on
524 * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
525 * bits being set to 0xfffd according to the TRM.
526 *
527 * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
528 * approach once proper kernel integration made it mainline.
529 */
530 if (priv->reg == (void *)0x700b0400) {
531 mask = readl(&priv->reg->venmiscctl);
532 mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
533 writel(mask, &priv->reg->venmiscctl);
534 }
535#endif
536
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600537 priv->version = readw(&priv->reg->hcver);
538 debug("host version = %x\n", priv->version);
Tom Warren21ef6a12011-05-31 10:30:37 +0000539
540 /* mask all */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600541 writel(0xffffffff, &priv->reg->norintstsen);
542 writel(0xffffffff, &priv->reg->norintsigen);
Tom Warren21ef6a12011-05-31 10:30:37 +0000543
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600544 writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */
Tom Warren21ef6a12011-05-31 10:30:37 +0000545 /*
546 * NORMAL Interrupt Status Enable Register init
547 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
548 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
Anton staaf5a762e22011-11-10 11:56:50 +0000549 * [3] ENSTADMAINT : DMA boundary interrupt
Tom Warren21ef6a12011-05-31 10:30:37 +0000550 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
551 * [0] ENSTACMDCMPLT : Command Complete Status Enable
552 */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600553 mask = readl(&priv->reg->norintstsen);
Tom Warren21ef6a12011-05-31 10:30:37 +0000554 mask &= ~(0xffff);
Anton staaf8e42f0d2011-11-10 11:56:49 +0000555 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
556 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
Anton staaf5a762e22011-11-10 11:56:50 +0000557 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
Anton staaf8e42f0d2011-11-10 11:56:49 +0000558 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
559 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600560 writel(mask, &priv->reg->norintstsen);
Tom Warren21ef6a12011-05-31 10:30:37 +0000561
562 /*
563 * NORMAL Interrupt Signal Enable Register init
564 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
565 */
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600566 mask = readl(&priv->reg->norintsigen);
Tom Warren21ef6a12011-05-31 10:30:37 +0000567 mask &= ~(0xffff);
Anton staaf8e42f0d2011-11-10 11:56:49 +0000568 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600569 writel(mask, &priv->reg->norintsigen);
Tom Warren21ef6a12011-05-31 10:30:37 +0000570
571 return 0;
572}
573
Simon Glass0e513e72017-04-23 20:02:11 -0600574static int tegra_mmc_getcd(struct udevice *dev)
Thierry Redingbf836622012-01-02 01:15:39 +0000575{
Simon Glass0e513e72017-04-23 20:02:11 -0600576 struct tegra_mmc_priv *priv = dev_get_priv(dev);
Thierry Redingbf836622012-01-02 01:15:39 +0000577
Tom Warren29f3e3f2012-09-04 17:00:24 -0700578 debug("tegra_mmc_getcd called\n");
Thierry Redingbf836622012-01-02 01:15:39 +0000579
Stephen Warrenf53c4e42016-09-13 10:45:46 -0600580 if (dm_gpio_is_valid(&priv->cd_gpio))
581 return dm_gpio_get_value(&priv->cd_gpio);
Thierry Redingbf836622012-01-02 01:15:39 +0000582
583 return 1;
584}
585
Simon Glass0e513e72017-04-23 20:02:11 -0600586static const struct dm_mmc_ops tegra_mmc_ops = {
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200587 .send_cmd = tegra_mmc_send_cmd,
588 .set_ios = tegra_mmc_set_ios,
Simon Glass0e513e72017-04-23 20:02:11 -0600589 .get_cd = tegra_mmc_getcd,
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200590};
591
Tom Warren6a474db2016-09-13 10:45:48 -0600592static int tegra_mmc_probe(struct udevice *dev)
Tom Warren21ef6a12011-05-31 10:30:37 +0000593{
Tom Warren6a474db2016-09-13 10:45:48 -0600594 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glass0e513e72017-04-23 20:02:11 -0600595 struct tegra_mmc_plat *plat = dev_get_platdata(dev);
Tom Warren6a474db2016-09-13 10:45:48 -0600596 struct tegra_mmc_priv *priv = dev_get_priv(dev);
Simon Glass0e513e72017-04-23 20:02:11 -0600597 struct mmc_config *cfg = &plat->cfg;
Stephen Warrene8adca92016-09-13 10:46:01 -0600598 int bus_width, ret;
Tom Warren21ef6a12011-05-31 10:30:37 +0000599
Simon Glass0e513e72017-04-23 20:02:11 -0600600 cfg->name = dev->name;
Tom Warren21ef6a12011-05-31 10:30:37 +0000601
Simon Glass49cb9302017-07-25 08:30:08 -0600602 bus_width = dev_read_u32_default(dev, "bus-width", 1);
Tom Warren6a474db2016-09-13 10:45:48 -0600603
Simon Glass0e513e72017-04-23 20:02:11 -0600604 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
605 cfg->host_caps = 0;
Tom Warren6a474db2016-09-13 10:45:48 -0600606 if (bus_width == 8)
Simon Glass0e513e72017-04-23 20:02:11 -0600607 cfg->host_caps |= MMC_MODE_8BIT;
Tom Warren6a474db2016-09-13 10:45:48 -0600608 if (bus_width >= 4)
Simon Glass0e513e72017-04-23 20:02:11 -0600609 cfg->host_caps |= MMC_MODE_4BIT;
610 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
Tom Warren21ef6a12011-05-31 10:30:37 +0000611
612 /*
613 * min freq is for card identification, and is the highest
614 * low-speed SDIO card frequency (actually 400KHz)
615 * max freq is highest HS eMMC clock as per the SD/MMC spec
616 * (actually 52MHz)
Tom Warren21ef6a12011-05-31 10:30:37 +0000617 */
Simon Glass0e513e72017-04-23 20:02:11 -0600618 cfg->f_min = 375000;
619 cfg->f_max = 48000000;
Tom Warren21ef6a12011-05-31 10:30:37 +0000620
Simon Glass0e513e72017-04-23 20:02:11 -0600621 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200622
Simon Glass49cb9302017-07-25 08:30:08 -0600623 priv->reg = (void *)dev_read_addr(dev);
Tom Warrenc9aa8312013-02-21 12:31:30 +0000624
Tom Warren6a474db2016-09-13 10:45:48 -0600625 ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
626 if (ret) {
627 debug("reset_get_by_name() failed: %d\n", ret);
628 return ret;
Stephen Warrenc0493072016-08-05 16:10:33 -0600629 }
Tom Warren6a474db2016-09-13 10:45:48 -0600630 ret = clk_get_by_index(dev, 0, &priv->clk);
631 if (ret) {
632 debug("clk_get_by_index() failed: %d\n", ret);
633 return ret;
634 }
635
636 ret = reset_assert(&priv->reset_ctl);
637 if (ret)
638 return ret;
639 ret = clk_enable(&priv->clk);
640 if (ret)
641 return ret;
642 ret = clk_set_rate(&priv->clk, 20000000);
643 if (IS_ERR_VALUE(ret))
644 return ret;
645 ret = reset_deassert(&priv->reset_ctl);
646 if (ret)
647 return ret;
Tom Warrenc9aa8312013-02-21 12:31:30 +0000648
649 /* These GPIOs are optional */
Simon Glass49cb9302017-07-25 08:30:08 -0600650 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
651 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
652 gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
653 GPIOD_IS_OUT);
Tom Warren6a474db2016-09-13 10:45:48 -0600654 if (dm_gpio_is_valid(&priv->pwr_gpio))
655 dm_gpio_set_value(&priv->pwr_gpio, 1);
Tom Warrenc9aa8312013-02-21 12:31:30 +0000656
Simon Glass0e513e72017-04-23 20:02:11 -0600657 upriv->mmc = &plat->mmc;
Tom Warren6a474db2016-09-13 10:45:48 -0600658
Simon Glass0e513e72017-04-23 20:02:11 -0600659 return tegra_mmc_init(dev);
660}
Tom Warren6a474db2016-09-13 10:45:48 -0600661
Simon Glass0e513e72017-04-23 20:02:11 -0600662static int tegra_mmc_bind(struct udevice *dev)
663{
664 struct tegra_mmc_plat *plat = dev_get_platdata(dev);
665
666 return mmc_bind(dev, &plat->mmc, &plat->cfg);
Tom Warrenc9aa8312013-02-21 12:31:30 +0000667}
668
Tom Warren6a474db2016-09-13 10:45:48 -0600669static const struct udevice_id tegra_mmc_ids[] = {
670 { .compatible = "nvidia,tegra20-sdhci" },
671 { .compatible = "nvidia,tegra30-sdhci" },
672 { .compatible = "nvidia,tegra114-sdhci" },
673 { .compatible = "nvidia,tegra124-sdhci" },
674 { .compatible = "nvidia,tegra210-sdhci" },
675 { .compatible = "nvidia,tegra186-sdhci" },
676 { }
677};
Tom Warrenc9aa8312013-02-21 12:31:30 +0000678
Tom Warren6a474db2016-09-13 10:45:48 -0600679U_BOOT_DRIVER(tegra_mmc_drv) = {
680 .name = "tegra_mmc",
681 .id = UCLASS_MMC,
682 .of_match = tegra_mmc_ids,
Simon Glass0e513e72017-04-23 20:02:11 -0600683 .bind = tegra_mmc_bind,
Tom Warren6a474db2016-09-13 10:45:48 -0600684 .probe = tegra_mmc_probe,
Simon Glass0e513e72017-04-23 20:02:11 -0600685 .ops = &tegra_mmc_ops,
686 .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat),
Tom Warren6a474db2016-09-13 10:45:48 -0600687 .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
688};