blob: 89d4a5e9ccacf5d49d7ca9f26d07983f3f01f211 [file] [log] [blame]
Simon Glasseffcf062014-11-14 20:56:36 -07001/*
2 * From Coreboot file of the same name
3 *
4 * Copyright (C) 2011 Chromium OS Authors
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9#include <common.h>
10#include <bios_emul.h>
11#include <errno.h>
12#include <fdtdec.h>
13#include <pci_rom.h>
14#include <asm/io.h>
Simon Glass9818a002015-01-01 16:18:08 -070015#include <asm/mtrr.h>
Simon Glasseffcf062014-11-14 20:56:36 -070016#include <asm/pci.h>
17#include <asm/arch/pch.h>
18#include <asm/arch/sandybridge.h>
19
20struct gt_powermeter {
21 u16 reg;
22 u32 value;
23};
24
25static const struct gt_powermeter snb_pm_gt1[] = {
26 { 0xa200, 0xcc000000 },
27 { 0xa204, 0x07000040 },
28 { 0xa208, 0x0000fe00 },
29 { 0xa20c, 0x00000000 },
30 { 0xa210, 0x17000000 },
31 { 0xa214, 0x00000021 },
32 { 0xa218, 0x0817fe19 },
33 { 0xa21c, 0x00000000 },
34 { 0xa220, 0x00000000 },
35 { 0xa224, 0xcc000000 },
36 { 0xa228, 0x07000040 },
37 { 0xa22c, 0x0000fe00 },
38 { 0xa230, 0x00000000 },
39 { 0xa234, 0x17000000 },
40 { 0xa238, 0x00000021 },
41 { 0xa23c, 0x0817fe19 },
42 { 0xa240, 0x00000000 },
43 { 0xa244, 0x00000000 },
44 { 0xa248, 0x8000421e },
45 { 0 }
46};
47
48static const struct gt_powermeter snb_pm_gt2[] = {
49 { 0xa200, 0x330000a6 },
50 { 0xa204, 0x402d0031 },
51 { 0xa208, 0x00165f83 },
52 { 0xa20c, 0xf1000000 },
53 { 0xa210, 0x00000000 },
54 { 0xa214, 0x00160016 },
55 { 0xa218, 0x002a002b },
56 { 0xa21c, 0x00000000 },
57 { 0xa220, 0x00000000 },
58 { 0xa224, 0x330000a6 },
59 { 0xa228, 0x402d0031 },
60 { 0xa22c, 0x00165f83 },
61 { 0xa230, 0xf1000000 },
62 { 0xa234, 0x00000000 },
63 { 0xa238, 0x00160016 },
64 { 0xa23c, 0x002a002b },
65 { 0xa240, 0x00000000 },
66 { 0xa244, 0x00000000 },
67 { 0xa248, 0x8000421e },
68 { 0 }
69};
70
71static const struct gt_powermeter ivb_pm_gt1[] = {
72 { 0xa800, 0x00000000 },
73 { 0xa804, 0x00021c00 },
74 { 0xa808, 0x00000403 },
75 { 0xa80c, 0x02001700 },
76 { 0xa810, 0x05000200 },
77 { 0xa814, 0x00000000 },
78 { 0xa818, 0x00690500 },
79 { 0xa81c, 0x0000007f },
80 { 0xa820, 0x01002501 },
81 { 0xa824, 0x00000300 },
82 { 0xa828, 0x01000331 },
83 { 0xa82c, 0x0000000c },
84 { 0xa830, 0x00010016 },
85 { 0xa834, 0x01100101 },
86 { 0xa838, 0x00010103 },
87 { 0xa83c, 0x00041300 },
88 { 0xa840, 0x00000b30 },
89 { 0xa844, 0x00000000 },
90 { 0xa848, 0x7f000000 },
91 { 0xa84c, 0x05000008 },
92 { 0xa850, 0x00000001 },
93 { 0xa854, 0x00000004 },
94 { 0xa858, 0x00000007 },
95 { 0xa85c, 0x00000000 },
96 { 0xa860, 0x00010000 },
97 { 0xa248, 0x0000221e },
98 { 0xa900, 0x00000000 },
99 { 0xa904, 0x00001c00 },
100 { 0xa908, 0x00000000 },
101 { 0xa90c, 0x06000000 },
102 { 0xa910, 0x09000200 },
103 { 0xa914, 0x00000000 },
104 { 0xa918, 0x00590000 },
105 { 0xa91c, 0x00000000 },
106 { 0xa920, 0x04002501 },
107 { 0xa924, 0x00000100 },
108 { 0xa928, 0x03000410 },
109 { 0xa92c, 0x00000000 },
110 { 0xa930, 0x00020000 },
111 { 0xa934, 0x02070106 },
112 { 0xa938, 0x00010100 },
113 { 0xa93c, 0x00401c00 },
114 { 0xa940, 0x00000000 },
115 { 0xa944, 0x00000000 },
116 { 0xa948, 0x10000e00 },
117 { 0xa94c, 0x02000004 },
118 { 0xa950, 0x00000001 },
119 { 0xa954, 0x00000004 },
120 { 0xa960, 0x00060000 },
121 { 0xaa3c, 0x00001c00 },
122 { 0xaa54, 0x00000004 },
123 { 0xaa60, 0x00060000 },
124 { 0 }
125};
126
127static const struct gt_powermeter ivb_pm_gt2[] = {
128 { 0xa800, 0x10000000 },
129 { 0xa804, 0x00033800 },
130 { 0xa808, 0x00000902 },
131 { 0xa80c, 0x0c002f00 },
132 { 0xa810, 0x12000400 },
133 { 0xa814, 0x00000000 },
134 { 0xa818, 0x00d20800 },
135 { 0xa81c, 0x00000002 },
136 { 0xa820, 0x03004b02 },
137 { 0xa824, 0x00000600 },
138 { 0xa828, 0x07000773 },
139 { 0xa82c, 0x00000000 },
140 { 0xa830, 0x00010032 },
141 { 0xa834, 0x1520040d },
142 { 0xa838, 0x00020105 },
143 { 0xa83c, 0x00083700 },
144 { 0xa840, 0x0000151d },
145 { 0xa844, 0x00000000 },
146 { 0xa848, 0x20001b00 },
147 { 0xa84c, 0x0a000010 },
148 { 0xa850, 0x00000000 },
149 { 0xa854, 0x00000008 },
150 { 0xa858, 0x00000008 },
151 { 0xa85c, 0x00000000 },
152 { 0xa860, 0x00020000 },
153 { 0xa248, 0x0000221e },
154 { 0xa900, 0x00000000 },
155 { 0xa904, 0x00003500 },
156 { 0xa908, 0x00000000 },
157 { 0xa90c, 0x0c000000 },
158 { 0xa910, 0x12000500 },
159 { 0xa914, 0x00000000 },
160 { 0xa918, 0x00b20000 },
161 { 0xa91c, 0x00000000 },
162 { 0xa920, 0x08004b02 },
163 { 0xa924, 0x00000200 },
164 { 0xa928, 0x07000820 },
165 { 0xa92c, 0x00000000 },
166 { 0xa930, 0x00030000 },
167 { 0xa934, 0x050f020d },
168 { 0xa938, 0x00020300 },
169 { 0xa93c, 0x00903900 },
170 { 0xa940, 0x00000000 },
171 { 0xa944, 0x00000000 },
172 { 0xa948, 0x20001b00 },
173 { 0xa94c, 0x0a000010 },
174 { 0xa950, 0x00000000 },
175 { 0xa954, 0x00000008 },
176 { 0xa960, 0x00110000 },
177 { 0xaa3c, 0x00003900 },
178 { 0xaa54, 0x00000008 },
179 { 0xaa60, 0x00110000 },
180 { 0 }
181};
182
183static const struct gt_powermeter ivb_pm_gt2_17w[] = {
184 { 0xa800, 0x20000000 },
185 { 0xa804, 0x000e3800 },
186 { 0xa808, 0x00000806 },
187 { 0xa80c, 0x0c002f00 },
188 { 0xa810, 0x0c000800 },
189 { 0xa814, 0x00000000 },
190 { 0xa818, 0x00d20d00 },
191 { 0xa81c, 0x000000ff },
192 { 0xa820, 0x03004b02 },
193 { 0xa824, 0x00000600 },
194 { 0xa828, 0x07000773 },
195 { 0xa82c, 0x00000000 },
196 { 0xa830, 0x00020032 },
197 { 0xa834, 0x1520040d },
198 { 0xa838, 0x00020105 },
199 { 0xa83c, 0x00083700 },
200 { 0xa840, 0x000016ff },
201 { 0xa844, 0x00000000 },
202 { 0xa848, 0xff000000 },
203 { 0xa84c, 0x0a000010 },
204 { 0xa850, 0x00000002 },
205 { 0xa854, 0x00000008 },
206 { 0xa858, 0x0000000f },
207 { 0xa85c, 0x00000000 },
208 { 0xa860, 0x00020000 },
209 { 0xa248, 0x0000221e },
210 { 0xa900, 0x00000000 },
211 { 0xa904, 0x00003800 },
212 { 0xa908, 0x00000000 },
213 { 0xa90c, 0x0c000000 },
214 { 0xa910, 0x12000800 },
215 { 0xa914, 0x00000000 },
216 { 0xa918, 0x00b20000 },
217 { 0xa91c, 0x00000000 },
218 { 0xa920, 0x08004b02 },
219 { 0xa924, 0x00000300 },
220 { 0xa928, 0x01000820 },
221 { 0xa92c, 0x00000000 },
222 { 0xa930, 0x00030000 },
223 { 0xa934, 0x15150406 },
224 { 0xa938, 0x00020300 },
225 { 0xa93c, 0x00903900 },
226 { 0xa940, 0x00000000 },
227 { 0xa944, 0x00000000 },
228 { 0xa948, 0x20001b00 },
229 { 0xa94c, 0x0a000010 },
230 { 0xa950, 0x00000000 },
231 { 0xa954, 0x00000008 },
232 { 0xa960, 0x00110000 },
233 { 0xaa3c, 0x00003900 },
234 { 0xaa54, 0x00000008 },
235 { 0xaa60, 0x00110000 },
236 { 0 }
237};
238
239static const struct gt_powermeter ivb_pm_gt2_35w[] = {
240 { 0xa800, 0x00000000 },
241 { 0xa804, 0x00030400 },
242 { 0xa808, 0x00000806 },
243 { 0xa80c, 0x0c002f00 },
244 { 0xa810, 0x0c000300 },
245 { 0xa814, 0x00000000 },
246 { 0xa818, 0x00d20d00 },
247 { 0xa81c, 0x000000ff },
248 { 0xa820, 0x03004b02 },
249 { 0xa824, 0x00000600 },
250 { 0xa828, 0x07000773 },
251 { 0xa82c, 0x00000000 },
252 { 0xa830, 0x00020032 },
253 { 0xa834, 0x1520040d },
254 { 0xa838, 0x00020105 },
255 { 0xa83c, 0x00083700 },
256 { 0xa840, 0x000016ff },
257 { 0xa844, 0x00000000 },
258 { 0xa848, 0xff000000 },
259 { 0xa84c, 0x0a000010 },
260 { 0xa850, 0x00000001 },
261 { 0xa854, 0x00000008 },
262 { 0xa858, 0x00000008 },
263 { 0xa85c, 0x00000000 },
264 { 0xa860, 0x00020000 },
265 { 0xa248, 0x0000221e },
266 { 0xa900, 0x00000000 },
267 { 0xa904, 0x00003800 },
268 { 0xa908, 0x00000000 },
269 { 0xa90c, 0x0c000000 },
270 { 0xa910, 0x12000800 },
271 { 0xa914, 0x00000000 },
272 { 0xa918, 0x00b20000 },
273 { 0xa91c, 0x00000000 },
274 { 0xa920, 0x08004b02 },
275 { 0xa924, 0x00000300 },
276 { 0xa928, 0x01000820 },
277 { 0xa92c, 0x00000000 },
278 { 0xa930, 0x00030000 },
279 { 0xa934, 0x15150406 },
280 { 0xa938, 0x00020300 },
281 { 0xa93c, 0x00903900 },
282 { 0xa940, 0x00000000 },
283 { 0xa944, 0x00000000 },
284 { 0xa948, 0x20001b00 },
285 { 0xa94c, 0x0a000010 },
286 { 0xa950, 0x00000000 },
287 { 0xa954, 0x00000008 },
288 { 0xa960, 0x00110000 },
289 { 0xaa3c, 0x00003900 },
290 { 0xaa54, 0x00000008 },
291 { 0xaa60, 0x00110000 },
292 { 0 }
293};
294
295/*
296 * Some vga option roms are used for several chipsets but they only have one
297 * PCI ID in their header. If we encounter such an option rom, we need to do
298 * the mapping ourselves.
299 */
300
301u32 map_oprom_vendev(u32 vendev)
302{
303 u32 new_vendev = vendev;
304
305 switch (vendev) {
306 case 0x80860102: /* GT1 Desktop */
307 case 0x8086010a: /* GT1 Server */
308 case 0x80860112: /* GT2 Desktop */
309 case 0x80860116: /* GT2 Mobile */
310 case 0x80860122: /* GT2 Desktop >=1.3GHz */
311 case 0x80860126: /* GT2 Mobile >=1.3GHz */
312 case 0x80860156: /* IVB */
313 case 0x80860166: /* IVB */
314 /* Set to GT1 Mobile */
315 new_vendev = 0x80860106;
316 break;
317 }
318
319 return new_vendev;
320}
321
322static inline u32 gtt_read(void *bar, u32 reg)
323{
324 return readl(bar + reg);
325}
326
327static inline void gtt_write(void *bar, u32 reg, u32 data)
328{
329 writel(data, bar + reg);
330}
331
332static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
333{
334 for (; pm && pm->reg; pm++)
335 gtt_write(bar, pm->reg, pm->value);
336}
337
338#define GTT_RETRY 1000
339static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
340{
341 unsigned try = GTT_RETRY;
342 u32 data;
343
344 while (try--) {
345 data = gtt_read(bar, reg);
346 if ((data & mask) == value)
347 return 1;
348 udelay(10);
349 }
350
351 printf("GT init timeout\n");
352 return 0;
353}
354
355static int gma_pm_init_pre_vbios(void *gtt_bar)
356{
357 u32 reg32;
358
359 debug("GT Power Management Init, silicon = %#x\n",
360 bridge_silicon_revision());
361
362 if (bridge_silicon_revision() < IVB_STEP_C0) {
363 /* 1: Enable force wake */
364 gtt_write(gtt_bar, 0xa18c, 0x00000001);
365 gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
366 } else {
367 gtt_write(gtt_bar, 0xa180, 1 << 5);
368 gtt_write(gtt_bar, 0xa188, 0xffff0001);
369 gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
370 }
371
372 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
373 /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
374 reg32 = gtt_read(gtt_bar, 0x42004);
375 reg32 |= (1 << 14) | (1 << 15);
376 gtt_write(gtt_bar, 0x42004, reg32);
377 }
378
379 if (bridge_silicon_revision() >= IVB_STEP_A0) {
380 /* Display Reset Acknowledge Settings */
381 reg32 = gtt_read(gtt_bar, 0x45010);
382 reg32 |= (1 << 1) | (1 << 0);
383 gtt_write(gtt_bar, 0x45010, reg32);
384 }
385
386 /* 2: Get GT SKU from GTT+0x911c[13] */
387 reg32 = gtt_read(gtt_bar, 0x911c);
388 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
389 if (reg32 & (1 << 13)) {
390 debug("SNB GT1 Power Meter Weights\n");
391 gtt_write_powermeter(gtt_bar, snb_pm_gt1);
392 } else {
393 debug("SNB GT2 Power Meter Weights\n");
394 gtt_write_powermeter(gtt_bar, snb_pm_gt2);
395 }
396 } else {
397 u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
398
399 if (reg32 & (1 << 13)) {
400 /* GT1 SKU */
401 debug("IVB GT1 Power Meter Weights\n");
402 gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
403 } else {
404 /* GT2 SKU */
405 u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
406 tdp /= (1 << unit);
407
408 if (tdp <= 17) {
409 /* <=17W ULV */
410 debug("IVB GT2 17W Power Meter Weights\n");
411 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
412 } else if ((tdp >= 25) && (tdp <= 35)) {
413 /* 25W-35W */
414 debug("IVB GT2 25W-35W Power Meter Weights\n");
415 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
416 } else {
417 /* All others */
418 debug("IVB GT2 35W Power Meter Weights\n");
419 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
420 }
421 }
422 }
423
424 /* 3: Gear ratio map */
425 gtt_write(gtt_bar, 0xa004, 0x00000010);
426
427 /* 4: GFXPAUSE */
428 gtt_write(gtt_bar, 0xa000, 0x00070020);
429
430 /* 5: Dynamic EU trip control */
431 gtt_write(gtt_bar, 0xa080, 0x00000004);
432
433 /* 6: ECO bits */
434 reg32 = gtt_read(gtt_bar, 0xa180);
435 reg32 |= (1 << 26) | (1 << 31);
436 /* (bit 20=1 for SNB step D1+ / IVB A0+) */
437 if (bridge_silicon_revision() >= SNB_STEP_D1)
438 reg32 |= (1 << 20);
439 gtt_write(gtt_bar, 0xa180, reg32);
440
441 /* 6a: for SnB step D2+ only */
442 if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
443 (bridge_silicon_revision() >= SNB_STEP_D2)) {
444 reg32 = gtt_read(gtt_bar, 0x9400);
445 reg32 |= (1 << 7);
446 gtt_write(gtt_bar, 0x9400, reg32);
447
448 reg32 = gtt_read(gtt_bar, 0x941c);
449 reg32 &= 0xf;
450 reg32 |= (1 << 1);
451 gtt_write(gtt_bar, 0x941c, reg32);
452 gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
453 }
454
455 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
456 reg32 = gtt_read(gtt_bar, 0x907c);
457 reg32 |= (1 << 16);
458 gtt_write(gtt_bar, 0x907c, reg32);
459
460 /* 6b: Clocking reset controls */
461 gtt_write(gtt_bar, 0x9424, 0x00000001);
462 } else {
463 /* 6b: Clocking reset controls */
464 gtt_write(gtt_bar, 0x9424, 0x00000000);
465 }
466
467 /* 7 */
468 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
469 gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
470 /* Mailbox Cmd for RC6 VID */
471 gtt_write(gtt_bar, 0x138124, 0x80000004);
472 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
473 gtt_write(gtt_bar, 0x138124, 0x8000000a);
474 gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
475 }
476
477 /* 8 */
478 gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
479 gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
480 gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
481 gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
482 gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
483 gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
484
485 /* 9 */
486 gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
487 gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
488 gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
489
490 /* 10 */
491 gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
492 gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
493 gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
494 gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
495 gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
496
497 /* 11 */
498 gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
499 gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
500 gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
501 gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
502 gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
503 gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
504 gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
505
506 /* 11a: Enable Render Standby (RC6) */
507 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
508 /*
509 * IvyBridge should also support DeepRenderStandby.
510 *
511 * Unfortunately it does not work reliably on all SKUs so
512 * disable it here and it can be enabled by the kernel.
513 */
514 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
515 } else {
516 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
517 }
518
519 /* 12: Normal Frequency Request */
520 /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
521 reg32 = readl(MCHBAR_REG(0x5998));
522 reg32 >>= 16;
523 reg32 &= 0xef;
524 reg32 <<= 25;
525 gtt_write(gtt_bar, 0xa008, reg32);
526
527 /* 13: RP Control */
528 gtt_write(gtt_bar, 0xa024, 0x00000592);
529
530 /* 14: Enable PM Interrupts */
531 gtt_write(gtt_bar, 0x4402c, 0x03000076);
532
533 /* Clear 0x6c024 [8:6] */
534 reg32 = gtt_read(gtt_bar, 0x6c024);
535 reg32 &= ~0x000001c0;
536 gtt_write(gtt_bar, 0x6c024, reg32);
537
538 return 0;
539}
540
541int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node)
542{
543 u32 reg32, cycle_delay;
544
545 debug("GT Power Management Init (post VBIOS)\n");
546
547 /* 15: Deassert Force Wake */
548 if (bridge_silicon_revision() < IVB_STEP_C0) {
549 gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
550 gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
551 } else {
552 gtt_write(gtt_bar, 0xa188, 0x1fffe);
553 if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
554 gtt_write(gtt_bar, 0xa188,
555 gtt_read(gtt_bar, 0xa188) | 1);
556 }
557 }
558
559 /* 16: SW RC Control */
560 gtt_write(gtt_bar, 0xa094, 0x00060000);
561
562 /* Setup Digital Port Hotplug */
563 reg32 = gtt_read(gtt_bar, 0xc4030);
564 if (!reg32) {
565 u32 dp_hotplug[3];
566
567 if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
568 dp_hotplug, ARRAY_SIZE(dp_hotplug)))
569 return -EINVAL;
570
571 reg32 = (dp_hotplug[0] & 0x7) << 2;
572 reg32 |= (dp_hotplug[0] & 0x7) << 10;
573 reg32 |= (dp_hotplug[0] & 0x7) << 18;
574 gtt_write(gtt_bar, 0xc4030, reg32);
575 }
576
577 /* Setup Panel Power On Delays */
578 reg32 = gtt_read(gtt_bar, 0xc7208);
579 if (!reg32) {
580 reg32 = (unsigned)fdtdec_get_int(blob, node,
581 "panel-port-select", 0) << 30;
582 reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
583 << 16;
584 reg32 |= fdtdec_get_int(blob, node,
585 "panel-power-backlight-on-delay", 0);
586 gtt_write(gtt_bar, 0xc7208, reg32);
587 }
588
589 /* Setup Panel Power Off Delays */
590 reg32 = gtt_read(gtt_bar, 0xc720c);
591 if (!reg32) {
592 reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
593 << 16;
594 reg32 |= fdtdec_get_int(blob, node,
595 "panel-power-backlight-off-delay", 0);
596 gtt_write(gtt_bar, 0xc720c, reg32);
597 }
598
599 /* Setup Panel Power Cycle Delay */
600 cycle_delay = fdtdec_get_int(blob, node,
601 "intel,panel-power-cycle-delay", 0);
602 if (cycle_delay) {
603 reg32 = gtt_read(gtt_bar, 0xc7210);
604 reg32 &= ~0xff;
605 reg32 |= cycle_delay;
606 gtt_write(gtt_bar, 0xc7210, reg32);
607 }
608
609 /* Enable Backlight if needed */
610 reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
611 if (reg32) {
612 gtt_write(gtt_bar, 0x48250, (1 << 31));
613 gtt_write(gtt_bar, 0x48254, reg32);
614 }
615 reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
616 if (reg32) {
617 gtt_write(gtt_bar, 0xc8250, (1 << 31));
618 gtt_write(gtt_bar, 0xc8254, reg32);
619 }
620
621 return 0;
622}
623
624/*
625 * Some vga option roms are used for several chipsets but they only have one
626 * PCI ID in their header. If we encounter such an option rom, we need to do
627 * the mapping ourselves.
628 */
629
630uint32_t board_map_oprom_vendev(uint32_t vendev)
631{
632 switch (vendev) {
633 case 0x80860102: /* GT1 Desktop */
634 case 0x8086010a: /* GT1 Server */
635 case 0x80860112: /* GT2 Desktop */
636 case 0x80860116: /* GT2 Mobile */
637 case 0x80860122: /* GT2 Desktop >=1.3GHz */
638 case 0x80860126: /* GT2 Mobile >=1.3GHz */
639 case 0x80860156: /* IVB */
640 case 0x80860166: /* IVB */
641 return 0x80860106; /* GT1 Mobile */
642 }
643
644 return vendev;
645}
646
647static int int15_handler(void)
648{
649 int res = 0;
650
651 debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
652
653 switch (M.x86.R_AX) {
654 case 0x5f34:
655 /*
656 * Set Panel Fitting Hook:
657 * bit 2 = Graphics Stretching
658 * bit 1 = Text Stretching
659 * bit 0 = Centering (do not set with bit1 or bit2)
660 * 0 = video bios default
661 */
662 M.x86.R_AX = 0x005f;
663 M.x86.R_CL = 0x00; /* Use video bios default */
664 res = 1;
665 break;
666 case 0x5f35:
667 /*
668 * Boot Display Device Hook:
669 * bit 0 = CRT
670 * bit 1 = TV (eDP)
671 * bit 2 = EFP
672 * bit 3 = LFP
673 * bit 4 = CRT2
674 * bit 5 = TV2 (eDP)
675 * bit 6 = EFP2
676 * bit 7 = LFP2
677 */
678 M.x86.R_AX = 0x005f;
679 M.x86.R_CX = 0x0000; /* Use video bios default */
680 res = 1;
681 break;
682 case 0x5f51:
683 /*
684 * Hook to select active LFP configuration:
685 * 00h = No LVDS, VBIOS does not enable LVDS
686 * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
687 * 02h = SVDO-LVDS, LFP driven by SVDO decoder
688 * 03h = eDP, LFP Driven by Int-DisplayPort encoder
689 */
690 M.x86.R_AX = 0x005f;
691 M.x86.R_CX = 0x0003; /* eDP */
692 res = 1;
693 break;
694 case 0x5f70:
695 switch (M.x86.R_CH) {
696 case 0:
697 /* Get Mux */
698 M.x86.R_AX = 0x005f;
699 M.x86.R_CX = 0x0000;
700 res = 1;
701 break;
702 case 1:
703 /* Set Mux */
704 M.x86.R_AX = 0x005f;
705 M.x86.R_CX = 0x0000;
706 res = 1;
707 break;
708 case 2:
709 /* Get SG/Non-SG mode */
710 M.x86.R_AX = 0x005f;
711 M.x86.R_CX = 0x0000;
712 res = 1;
713 break;
714 default:
715 /* Interrupt was not handled */
716 debug("Unknown INT15 5f70 function: 0x%02x\n",
717 M.x86.R_CH);
718 break;
719 }
720 break;
721 case 0x5fac:
722 res = 1;
723 break;
724 default:
725 debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
726 break;
727 }
728 return res;
729}
730
731int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
732 const void *blob, int node)
733{
Simon Glassd19ee5c2015-01-01 16:18:02 -0700734#ifdef CONFIG_VIDEO
735 ulong start;
736#endif
Simon Glasseffcf062014-11-14 20:56:36 -0700737 void *gtt_bar;
Simon Glass9818a002015-01-01 16:18:08 -0700738 ulong base;
Simon Glasseffcf062014-11-14 20:56:36 -0700739 u32 reg32;
740 int ret;
741
742 /* IGD needs to be Bus Master */
Simon Glass31f57c22015-03-05 12:25:15 -0700743 reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
Simon Glasseffcf062014-11-14 20:56:36 -0700744 reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
Simon Glass31f57c22015-03-05 12:25:15 -0700745 x86_pci_write_config32(dev, PCI_COMMAND, reg32);
Simon Glasseffcf062014-11-14 20:56:36 -0700746
Simon Glass9818a002015-01-01 16:18:08 -0700747 /* Use write-combining for the graphics memory, 256MB */
748 base = pci_read_bar32(hose, dev, 2);
749 mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
750 mtrr_commit(true);
751
Simon Glasseffcf062014-11-14 20:56:36 -0700752 gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
753 debug("GT bar %p\n", gtt_bar);
754 ret = gma_pm_init_pre_vbios(gtt_bar);
755 if (ret)
756 return ret;
757
Simon Glassd19ee5c2015-01-01 16:18:02 -0700758#ifdef CONFIG_VIDEO
759 start = get_timer(0);
Simon Glassbc17d8f2015-01-27 22:13:34 -0700760 ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
761 PCI_ROM_ALLOW_FALLBACK);
Simon Glassd19ee5c2015-01-01 16:18:02 -0700762 debug("BIOS ran in %lums\n", get_timer(start));
763#endif
Simon Glasseffcf062014-11-14 20:56:36 -0700764 /* Post VBIOS init */
765 ret = gma_pm_init_post_vbios(gtt_bar, blob, node);
766 if (ret)
767 return ret;
768
769 return 0;
770}