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wdenk717b5aa2002-04-27 11:09:31 +00001/*
2 * NS16550 Serial Port
Stefan Roesea47a12b2010-04-15 16:07:28 +02003 * originally from linux source (arch/powerpc/boot/ns16550.h)
Detlev Zundel200779e2009-04-03 11:53:01 +02004 *
5 * Cleanup and unification
6 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
7 *
wdenk717b5aa2002-04-27 11:09:31 +00008 * modified slightly to
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02009 * have addresses as offsets from CONFIG_SYS_ISA_BASE
wdenk717b5aa2002-04-27 11:09:31 +000010 * added a few more definitions
11 * added prototypes for ns16550.c
12 * reduced no of com ports to 2
13 * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020014 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020015 * added support for port on 64-bit bus
16 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
wdenk717b5aa2002-04-27 11:09:31 +000017 */
18
Detlev Zundel453c0d72009-04-03 16:45:46 +020019/*
20 * Note that the following macro magic uses the fact that the compiler
21 * will not allocate storage for arrays of size 0
22 */
23
Dave Aldridge79df1202011-09-01 22:47:14 +000024#include <linux/types.h>
25
Detlev Zundel453c0d72009-04-03 16:45:46 +020026#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
wdenk717b5aa2002-04-27 11:09:31 +000027#error "Please define NS16550 registers size."
Dave Aldridge79df1202011-09-01 22:47:14 +000028#elif defined(CONFIG_SYS_NS16550_MEM32)
29#define UART_REG(x) u32 x
Detlev Zundel453c0d72009-04-03 16:45:46 +020030#elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
31#define UART_REG(x) \
32 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
33 unsigned char x;
34#elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
35#define UART_REG(x) \
36 unsigned char x; \
37 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
wdenk717b5aa2002-04-27 11:09:31 +000038#endif
39
Detlev Zundel453c0d72009-04-03 16:45:46 +020040struct NS16550 {
41 UART_REG(rbr); /* 0 */
42 UART_REG(ier); /* 1 */
43 UART_REG(fcr); /* 2 */
44 UART_REG(lcr); /* 3 */
45 UART_REG(mcr); /* 4 */
46 UART_REG(lsr); /* 5 */
47 UART_REG(msr); /* 6 */
48 UART_REG(spr); /* 7 */
Mikhail Kshevetskiy99b603e2012-07-09 08:52:43 +000049#ifdef CONFIG_SOC_DA8XX
50 UART_REG(reg8); /* 8 */
51 UART_REG(reg9); /* 9 */
52 UART_REG(revid1); /* A */
53 UART_REG(revid2); /* B */
54 UART_REG(pwr_mgmt); /* C */
55 UART_REG(mdr1); /* D */
56#else
Detlev Zundel453c0d72009-04-03 16:45:46 +020057 UART_REG(mdr1); /* 8 */
58 UART_REG(reg9); /* 9 */
59 UART_REG(regA); /* A */
60 UART_REG(regB); /* B */
61 UART_REG(regC); /* C */
62 UART_REG(regD); /* D */
63 UART_REG(regE); /* E */
64 UART_REG(uasr); /* F */
65 UART_REG(scr); /* 10*/
66 UART_REG(ssr); /* 11*/
67 UART_REG(reg12); /* 12*/
68 UART_REG(osc_12m_sel); /* 13*/
Mikhail Kshevetskiy99b603e2012-07-09 08:52:43 +000069#endif
Detlev Zundel453c0d72009-04-03 16:45:46 +020070};
71
wdenk717b5aa2002-04-27 11:09:31 +000072#define thr rbr
73#define iir fcr
74#define dll rbr
75#define dlm ier
76
Simon Glassf8df9d02011-10-15 19:14:09 +000077typedef struct NS16550 *NS16550_t;
wdenk717b5aa2002-04-27 11:09:31 +000078
Detlev Zundel200779e2009-04-03 11:53:01 +020079/*
80 * These are the definitions for the FIFO Control Register
81 */
Simon Glassf8df9d02011-10-15 19:14:09 +000082#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
Detlev Zundel200779e2009-04-03 11:53:01 +020083#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
84#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
85#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
86#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
87#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
88#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
89#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
90#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
wdenk717b5aa2002-04-27 11:09:31 +000091
Detlev Zundel200779e2009-04-03 11:53:01 +020092#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
93#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
wdenk717b5aa2002-04-27 11:09:31 +000094
Detlev Zundel200779e2009-04-03 11:53:01 +020095/*
96 * These are the definitions for the Modem Control Register
97 */
98#define UART_MCR_DTR 0x01 /* DTR */
99#define UART_MCR_RTS 0x02 /* RTS */
100#define UART_MCR_OUT1 0x04 /* Out 1 */
101#define UART_MCR_OUT2 0x08 /* Out 2 */
102#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
Karicheri, Muralidharand57dee52014-04-09 15:38:46 -0400103#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
wdenk717b5aa2002-04-27 11:09:31 +0000104
Detlev Zundel200779e2009-04-03 11:53:01 +0200105#define UART_MCR_DMA_EN 0x04
106#define UART_MCR_TX_DFR 0x08
wdenk717b5aa2002-04-27 11:09:31 +0000107
Detlev Zundel200779e2009-04-03 11:53:01 +0200108/*
109 * These are the definitions for the Line Control Register
110 *
111 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
112 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
113 */
114#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
115#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
116#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
117#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
118#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
Simon Glassf8df9d02011-10-15 19:14:09 +0000119#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
Detlev Zundel200779e2009-04-03 11:53:01 +0200120#define UART_LCR_PEN 0x08 /* Parity eneble */
121#define UART_LCR_EPS 0x10 /* Even Parity Select */
122#define UART_LCR_STKP 0x20 /* Stick Parity */
123#define UART_LCR_SBRK 0x40 /* Set Break */
124#define UART_LCR_BKSE 0x80 /* Bank select enable */
125#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
126
127/*
128 * These are the definitions for the Line Status Register
129 */
130#define UART_LSR_DR 0x01 /* Data ready */
131#define UART_LSR_OE 0x02 /* Overrun */
132#define UART_LSR_PE 0x04 /* Parity error */
133#define UART_LSR_FE 0x08 /* Framing error */
134#define UART_LSR_BI 0x10 /* Break */
135#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
136#define UART_LSR_TEMT 0x40 /* Xmitter empty */
137#define UART_LSR_ERR 0x80 /* Error */
138
139#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
140#define UART_MSR_RI 0x40 /* Ring Indicator */
141#define UART_MSR_DSR 0x20 /* Data Set Ready */
142#define UART_MSR_CTS 0x10 /* Clear to Send */
143#define UART_MSR_DDCD 0x08 /* Delta DCD */
144#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
145#define UART_MSR_DDSR 0x02 /* Delta DSR */
146#define UART_MSR_DCTS 0x01 /* Delta CTS */
147
148/*
149 * These are the definitions for the Interrupt Identification Register
150 */
151#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
152#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
153
154#define UART_IIR_MSI 0x00 /* Modem status interrupt */
155#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
156#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
157#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
158
159/*
160 * These are the definitions for the Interrupt Enable Register
161 */
162#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
163#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
164#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
165#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
166
Detlev Zundel7b5611c2009-03-30 00:31:34 +0200167
wdenk2e5983d2003-07-15 20:04:06 +0000168#ifdef CONFIG_OMAP1510
Detlev Zundel200779e2009-04-03 11:53:01 +0200169#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */
wdenk2e5983d2003-07-15 20:04:06 +0000170#endif
171
wdenk717b5aa2002-04-27 11:09:31 +0000172/* useful defaults for LCR */
Detlev Zundel200779e2009-04-03 11:53:01 +0200173#define UART_LCR_8N1 0x03
wdenk717b5aa2002-04-27 11:09:31 +0000174
Simon Glassf8df9d02011-10-15 19:14:09 +0000175void NS16550_init(NS16550_t com_port, int baud_divisor);
176void NS16550_putc(NS16550_t com_port, char c);
177char NS16550_getc(NS16550_t com_port);
178int NS16550_tstc(NS16550_t com_port);
179void NS16550_reinit(NS16550_t com_port, int baud_divisor);