blob: 1a43e1b433e553cc27a0254d40d78d4c0c4d5602 [file] [log] [blame]
Sonic Zhang320ec9d2012-08-16 12:08:31 +08001/*
2 * U-boot - Configuration file for BF609 EZ-Kit board
3 */
4
5#ifndef __CONFIG_BF609_EZKIT_H__
6#define __CONFIG_BF609_EZKIT_H__
7
8#include <asm/config-pre.h>
9
10/*
11 * Processor Settings
12 */
13#define CONFIG_BFIN_CPU bf609-0.0
14#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
15
16
17/* For ez-board version 1.0, else undef this */
18#define CONFIG_BFIN_BOARD_VERSION_1_0
19
20/*
21 * Clock Settings
22 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
23 * SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV
24 * SCLK0 = SCLK / SCLK0_DIV
25 * SCLK1 = SCLK / SCLK1_DIV
26 */
27/* CONFIG_CLKIN_HZ is any value in Hz */
28#define CONFIG_CLKIN_HZ (25000000)
29/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
30/* 1 = CLKIN / 2 */
31#define CONFIG_CLKIN_HALF (0)
32
33/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
34/* Values can range from 0-127 (where 0 means 128) */
35#define CONFIG_VCO_MULT (20)
36
37/* CCLK_DIV controls the core clock divider */
38/* Values can range from 0-31 (where 0 means 32) */
39#define CONFIG_CCLK_DIV (1)
40/* SCLK_DIV controls the system clock divider */
41/* Values can range from 0-31 (where 0 means 32) */
42#define CONFIG_SCLK_DIV (4)
43/* Values can range from 0-7 (where 0 means 8) */
44#define CONFIG_SCLK0_DIV (1)
45#define CONFIG_SCLK1_DIV (1)
46/* DCLK_DIV controls the DDR clock divider */
47/* Values can range from 0-31 (where 0 means 32) */
48#define CONFIG_DCLK_DIV (2)
49/* OCLK_DIV controls the output clock divider */
50/* Values can range from 0-127 (where 0 means 128) */
51#define CONFIG_OCLK_DIV (16)
52
53/*
54 * Memory Settings
55 */
56#define CONFIG_MEM_SIZE 128
57
58#define CONFIG_SMC_GCTL_VAL 0x00000010
59#define CONFIG_SMC_B0CTL_VAL 0x01007011
60#define CONFIG_SMC_B0TIM_VAL 0x08170977
61#define CONFIG_SMC_B0ETIM_VAL 0x00092231
62
63#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
64#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
65
Bob Liu49c2da52011-12-27 15:05:53 +080066#define CONFIG_HW_WATCHDOG
Sonic Zhang320ec9d2012-08-16 12:08:31 +080067/*
68 * Network Settings
69 */
70#define ADI_CMDS_NETWORK
71#define CONFIG_NETCONSOLE
72#define CONFIG_NET_MULTI
73#define CONFIG_HOSTNAME "bf609-ezkit"
74#define CONFIG_DESIGNWARE_ETH
75#define CONFIG_DW_PORTS 1
76#define CONFIG_DW_AUTONEG
77#define CONFIG_DW_ALTDESCRIPTOR
78#define CONFIG_CMD_NET
79#define CONFIG_CMD_MII
80#define CONFIG_MII
81
82/* i2c Settings */
83#define CONFIG_BFIN_TWI_I2C
84#define CONFIG_HARD_I2C
85
86/*
87 * Flash Settings
88 */
89#undef CONFIG_CMD_IMLS
90#undef CONFIG_CMD_JFFS2
91#define CONFIG_SYS_FLASH_CFI_WIDTH 2
92#define CONFIG_FLASH_CFI_DRIVER
93#define CONFIG_SYS_FLASH_BASE 0xb0000000
94#define CONFIG_SYS_FLASH_CFI
95#define CONFIG_SYS_FLASH_PROTECTION
96#define CONFIG_SYS_MAX_FLASH_BANKS 1
97#define CONFIG_SYS_MAX_FLASH_SECT 131
98#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
99
100/*
101 * SPI Settings
102 */
103#define CONFIG_BFIN_SPI6XX
104#define CONFIG_ENV_SPI_MAX_HZ 25000000
105#define CONFIG_SF_DEFAULT_SPEED 25000000
106#define CONFIG_SPI_FLASH
107#define CONFIG_SPI_FLASH_ALL
108
109/*
110 * Env Storage Settings
111 */
112#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
113#define CONFIG_ENV_IS_IN_SPI_FLASH
114#define CONFIG_ENV_OFFSET 0x10000
115#define CONFIG_ENV_SIZE 0x2000
116#define CONFIG_ENV_SECT_SIZE 0x10000
117#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
118#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
119#define CONFIG_ENV_IS_IN_NAND
120#define CONFIG_ENV_OFFSET 0x60000
121#define CONFIG_ENV_SIZE 0x20000
122#else
123#define CONFIG_ENV_IS_IN_FLASH
124#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
125#define CONFIG_ENV_OFFSET 0x8000
126#define CONFIG_ENV_SIZE 0x8000
127#define CONFIG_ENV_SECT_SIZE 0x8000
128#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
129#endif
130
131#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0"
132
133/*
134 * SDH Settings
135 */
136#define CONFIG_GENERIC_MMC
137#define CONFIG_MMC
138#define CONFIG_BFIN_SDH
139
140/*
141 * Misc Settings
142 */
143#define CONFIG_BOARD_EARLY_INIT_F
144#define CONFIG_UART_CONSOLE 0
145
146#define CONFIG_CMD_MEMORY
Bob Liu7d861d92013-02-05 19:05:41 +0800147#define CONFIG_CMD_SOFTSWITCH
Sonic Zhang320ec9d2012-08-16 12:08:31 +0800148
149#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
150#define CONFIG_BFIN_SOFT_SWITCH
151
Sonic Zhangda34aae2013-05-02 13:46:21 +0800152#define CONFIG_ADI_GPIO2
153
Sonic Zhang320ec9d2012-08-16 12:08:31 +0800154#if 0
155#define CONFIG_UART_MEM 1024
156#undef CONFIG_UART_CONSOLE
157#undef CONFIG_JTAG_CONSOLE
158#undef CONFIG_UART_CONSOLE_IS_JTAG
159#endif
160
Sonic Zhang955020c2013-02-20 18:05:16 +0800161#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024))
162
Sonic Zhang320ec9d2012-08-16 12:08:31 +0800163/*
Sonic Zhangf4d80382013-02-05 18:57:49 +0800164 * Run core 1 from L1 SRAM start address when init uboot on core 0
165 */
166/* #define CONFIG_CORE1_RUN 1 */
167
168/*
Sonic Zhang320ec9d2012-08-16 12:08:31 +0800169 * Pull in common ADI header for remaining command/environment setup
170 */
171#include <configs/bfin_adi_common.h>
172#endif