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Mingkai Huf3a8e2b2015-10-26 19:47:52 +08001/*
2 * Copyright 2015 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CPLD_H__
8#define __CPLD_H__
9
10/*
11 * CPLD register set of LS1043ARDB board-specific.
12 */
13struct cpld_data {
14 u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
15 u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
16 u8 pcba_ver; /* 0x2 - PCBA Revision Register */
17 u8 system_rst; /* 0x3 - system reset register */
18 u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
19 u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */
20 u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */
21 u8 vbank; /* 0x7 - Flash bank selection Control */
22 u8 sysclk_sel; /* 0x8 - */
23 u8 uart_sel; /* 0x9 - */
24 u8 sd1refclk_sel; /* 0xA - */
25 u8 tdmclk_mux_sel; /* 0xB - */
26 u8 sdhc_spics_sel; /* 0xC - */
27 u8 status_led; /* 0xD - */
28 u8 global_rst; /* 0xE - */
29};
30
31u8 cpld_read(unsigned int reg);
32void cpld_write(unsigned int reg, u8 value);
33void cpld_rev_bit(unsigned char *value);
34
35#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
36#define CPLD_WRITE(reg, value) \
37 cpld_write(offsetof(struct cpld_data, reg), value)
38
39/* CPLD on IFC */
40#define CPLD_SW_MUX_BANK_SEL 0x40
41#define CPLD_BANK_SEL_MASK 0x07
42#define CPLD_BANK_SEL_ALTBANK 0x04
Qianyu Gong869bf862016-04-25 16:38:35 +080043#define CPLD_CFG_RCW_SRC_NOR 0x025
Gong Qianyu3ad44722015-10-26 19:47:53 +080044#define CPLD_CFG_RCW_SRC_NAND 0x106
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080045#define CPLD_CFG_RCW_SRC_SD 0x040
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080046#endif