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Stefan Roese13b4f632012-08-14 15:04:19 +02001/*
Stefan Roese8aa34492013-04-25 23:20:23 +00002 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
Stefan Roese13b4f632012-08-14 15:04:19 +02003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese13b4f632012-08-14 15:04:19 +02005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10/*
11 * High Level Configuration Options
12 * (easy to change)
13 */
14
15#define CONFIG_MPC5200
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090016#define CONFIG_A3M071 /* A3M071 board */
Stefan Roese13b4f632012-08-14 15:04:19 +020017
18#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
19
Stefan Roesed4451d32013-02-07 02:10:11 +000020#define CONFIG_SPL_TARGET "u-boot-img.bin"
21
Stefan Roese13b4f632012-08-14 15:04:19 +020022#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
23
24#define CONFIG_MISC_INIT_R
25#define CONFIG_SYS_LOWBOOT /* Enable lowboot */
26
Stefan Roesed4451d32013-02-07 02:10:11 +000027#ifdef CONFIG_A4M2K
28#define CONFIG_HOSTNAME a4m2k
29#else
30#define CONFIG_HOSTNAME a3m071
31#endif
32
Stefan Roesed62a89b2013-06-22 16:16:25 +020033#define CONFIG_BOOTCOUNT_LIMIT
34
Stefan Roese13b4f632012-08-14 15:04:19 +020035/*
36 * Serial console configuration
37 */
38#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
Stefan Roese13b4f632012-08-14 15:04:19 +020039#define CONFIG_SYS_BAUDRATE_TABLE \
40 { 9600, 19200, 38400, 57600, 115200, 230400 }
41
42/*
43 * Command line configuration.
44 */
Stefan Roese13b4f632012-08-14 15:04:19 +020045#define CONFIG_CMD_REGINFO
Stefan Roese8aa34492013-04-25 23:20:23 +000046#define CONFIG_BOOTP_SEND_HOSTNAME
47#define CONFIG_BOOTP_SERVERIP
48#define CONFIG_BOOTP_MAY_FAIL
49#define CONFIG_BOOTP_BOOTPATH
50#define CONFIG_BOOTP_GATEWAY
51#define CONFIG_BOOTP_SERVERIP
52#define CONFIG_NET_RETRY_COUNT 3
Stefan Roese8aa34492013-04-25 23:20:23 +000053#define CONFIG_NETCONSOLE
Stefan Roese8aa34492013-04-25 23:20:23 +000054#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
55#define CONFIG_MTD_PARTITIONS /* needed for UBI */
56#define CONFIG_FLASH_CFI_MTD
57#define MTDIDS_DEFAULT "nor0=fc000000.flash"
58#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
Stefan Roesed62a89b2013-06-22 16:16:25 +020059 "128k(env1)," \
60 "128k(env2)," \
Stefan Roese8aa34492013-04-25 23:20:23 +000061 "128k(hwinfo)," \
62 "1M(nvramsim)," \
63 "128k(dtb)," \
64 "5M(kernel)," \
65 "128k(sysinfo)," \
66 "7552k(root)," \
67 "4M(app)," \
Stefan Roesed62a89b2013-06-22 16:16:25 +020068 "5376k(data)," \
69 "8M(install)"
70
Stefan Roese8aa34492013-04-25 23:20:23 +000071#define CONFIG_LZO /* needed for UBI */
72#define CONFIG_RBTREE /* needed for UBI */
73#define CONFIG_CMD_MTDPARTS
Stefan Roese8aa34492013-04-25 23:20:23 +000074#define CONFIG_CMD_UBIFS
Stefan Roese13b4f632012-08-14 15:04:19 +020075
76/*
77 * IPB Bus clocking configuration.
78 */
79#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
80/* define for 66MHz speed - undef for 33MHz PCI clock speed */
Stefan Roesed4451d32013-02-07 02:10:11 +000081#ifdef CONFIG_A4M2K
82#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
83#else
Stefan Roese13b4f632012-08-14 15:04:19 +020084#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Stefan Roesed4451d32013-02-07 02:10:11 +000085#endif
Stefan Roese13b4f632012-08-14 15:04:19 +020086
Stefan Roese13b4f632012-08-14 15:04:19 +020087/* maximum size of the flat tree (8K) */
88#define OF_FLAT_TREE_MAX_SIZE 8192
89
90#define OF_CPU "PowerPC,5200@0"
91#define OF_SOC "soc5200@f0000000"
92#define OF_TBCLK (bd->bi_busfreq / 4)
93#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
94
95/*
Stefan Roese13b4f632012-08-14 15:04:19 +020096 * NOR flash configuration
97 */
98#define CONFIG_SYS_FLASH_BASE 0xfc000000
Stefan Roesed4451d32013-02-07 02:10:11 +000099#define CONFIG_SYS_FLASH_SIZE 0x02000000
Stefan Roese8aa34492013-04-25 23:20:23 +0000100#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
Stefan Roese13b4f632012-08-14 15:04:19 +0200101
102#define CONFIG_SYS_MAX_FLASH_BANKS 1
103#define CONFIG_SYS_MAX_FLASH_SECT 256
104#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
105#define CONFIG_SYS_FLASH_WRITE_TOUT 500
106#define CONFIG_SYS_FLASH_LOCK_TOUT 5
107#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
108#define CONFIG_SYS_FLASH_PROTECTION
109#define CONFIG_FLASH_CFI_DRIVER
110#define CONFIG_SYS_FLASH_CFI
111#define CONFIG_SYS_FLASH_EMPTY_INFO
112#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Stefan Roesef8945512013-04-04 03:55:42 +0000113#define CONFIG_FLASH_VERIFY
Stefan Roese13b4f632012-08-14 15:04:19 +0200114
115/*
116 * Environment settings
117 */
118#define CONFIG_ENV_IS_IN_FLASH
119#define CONFIG_ENV_SIZE 0x10000
120#define CONFIG_ENV_SECT_SIZE 0x20000
121#define CONFIG_ENV_OVERWRITE
Stefan Roese8aa34492013-04-25 23:20:23 +0000122#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
123#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese13b4f632012-08-14 15:04:19 +0200124
125/*
126 * Memory map
127 */
128#define CONFIG_SYS_MBAR 0xf0000000
129#define CONFIG_SYS_SDRAM_BASE 0x00000000
130#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
131
132/* Use SRAM until RAM will be available */
133#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
York Sunb39d1212016-04-06 13:22:10 -0700134#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Stefan Roese13b4f632012-08-14 15:04:19 +0200135
York Sunb39d1212016-04-06 13:22:10 -0700136#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Stefan Roese704afcc2013-04-25 23:10:02 +0000137 GENERATED_GBL_DATA_SIZE)
Stefan Roese13b4f632012-08-14 15:04:19 +0200138#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
139
140#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
141
Stefan Roese8aa34492013-04-25 23:20:23 +0000142#define CONFIG_SYS_MONITOR_LEN (512 << 10)
143#define CONFIG_SYS_MALLOC_LEN (4 << 20)
Stefan Roese13b4f632012-08-14 15:04:19 +0200144#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
145
146/*
147 * Ethernet configuration
148 */
149#define CONFIG_MPC5xxx_FEC
150#define CONFIG_MPC5xxx_FEC_MII100
Stefan Roesed4451d32013-02-07 02:10:11 +0000151#ifdef CONFIG_A4M2K
152#define CONFIG_PHY_ADDR 0x01
153#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200154#define CONFIG_PHY_ADDR 0x00
Stefan Roesed4451d32013-02-07 02:10:11 +0000155#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200156
157/*
158 * GPIO configuration
159 */
160
161/*
162 * GPIO-config depends on failsave-level
163 * failsave 0 means just MPX-config, no digiboard, no fpga
164 * 1 means digiboard ok
165 * 2 means fpga ok
166 */
167
Stefan Roesed4451d32013-02-07 02:10:11 +0000168#ifdef CONFIG_A4M2K
Stefan Roese8aa34492013-04-25 23:20:23 +0000169#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
Stefan Roesed4451d32013-02-07 02:10:11 +0000170#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200171/* for failsave-level 0 - full failsave */
172#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
173/* for failsave-level 1 - only digiboard ok */
Stefan Roese8aa34492013-04-25 23:20:23 +0000174#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
Stefan Roese13b4f632012-08-14 15:04:19 +0200175/* for failsave-level 2 - all ok */
Stefan Roese8aa34492013-04-25 23:20:23 +0000176#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
Stefan Roesed4451d32013-02-07 02:10:11 +0000177#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200178
Stefan Roeseaed75482013-02-07 02:10:28 +0000179#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
180#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
181#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
182#endif
183
Stefan Roese13b4f632012-08-14 15:04:19 +0200184/*
185 * Configuration matrix
Stefan Roese8aa34492013-04-25 23:20:23 +0000186 * MSB LSB
Stefan Roesed4451d32013-02-07 02:10:11 +0000187 * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
Stefan Roese8aa34492013-04-25 23:20:23 +0000188 * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
189 * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
Stefan Roese13b4f632012-08-14 15:04:19 +0200190 * || ||| || | ||| | | | |
191 * || ||| || | ||| | | | | bit rev name
192 * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
193 * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
194 * ||| || | ||| | | | | 2 29 ALTs
195 * +++-++--+---+++-+---+---+---+- 3 28 ALTs
196 * ++-++--+---+++-+---+---+---+- 4 27 CS7
197 * +-++--+---+++-+---+---+---+- 5 26 CS6
198 * || | ||| | | | | 6 25 ATA
199 * ++--+---+++-+---+---+---+- 7 24 ATA
200 * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
201 * | ||| | | | | 9 22 IRDA
202 * | ||| | | | | 10 21 IRDA
203 * +---+++-+---+---+---+- 11 20 IRDA
204 * ||| | | | | 12 19 Ether
205 * ||| | | | | 13 18 Ether
206 * ||| | | | | 14 17 Ether
207 * +++-+---+---+---+- 15 16 Ether
208 * ++-+---+---+---+- 16 15 PCI_DIS
209 * +-+---+---+---+- 17 14 USB_SE
210 * | | | | 18 13 USB
211 * +---+---+---+- 19 12 USB
212 * | | | 20 11 PSC3
213 * | | | 21 10 PSC3
214 * | | | 22 9 PSC3
215 * +---+---+- 23 8 PSC3
216 * | | 24 7 -
217 * | | 25 6 PSC2
218 * | | 26 5 PSC2
219 * +---+- 27 4 PSC2
220 * | 28 3 -
221 * | 29 2 PSC1
222 * | 30 1 PSC1
223 * +- 31 0 PSC1
224 */
225
Stefan Roese13b4f632012-08-14 15:04:19 +0200226/*
227 * Miscellaneous configurable options
228 */
229#define CONFIG_SYS_LONGHELP
Stefan Roese13b4f632012-08-14 15:04:19 +0200230
231#define CONFIG_CMDLINE_EDITING
Stefan Roese13b4f632012-08-14 15:04:19 +0200232
233#if defined(CONFIG_CMD_KGDB)
234#define CONFIG_SYS_CBSIZE 1024
235#else
236#define CONFIG_SYS_CBSIZE 256
237#endif
238#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
239#define CONFIG_SYS_MAXARGS 16
240#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
241
242#define CONFIG_SYS_MEMTEST_START 0x00100000
243#define CONFIG_SYS_MEMTEST_END 0x00f00000
244
245#define CONFIG_SYS_LOAD_ADDR 0x00100000
246
Stefan Roese13b4f632012-08-14 15:04:19 +0200247/*
248 * Various low-level settings
249 */
250#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
251#define CONFIG_SYS_HID0_FINAL HID0_ICE
252
253#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
254#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
255#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
256#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Stefan Roesed4451d32013-02-07 02:10:11 +0000257
258#ifdef CONFIG_A4M2K
259/* external MRAM */
260#define CONFIG_SYS_CS1_START 0xf1000000
261#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
262#endif
263
Stefan Roese13b4f632012-08-14 15:04:19 +0200264#define CONFIG_SYS_CS2_START 0xe0000000
265#define CONFIG_SYS_CS2_SIZE 0x00100000
266
Stefan Roesed4451d32013-02-07 02:10:11 +0000267/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
Stefan Roese13b4f632012-08-14 15:04:19 +0200268#define CONFIG_SYS_CS3_START 0xE9000000
Stefan Roesed4451d32013-02-07 02:10:11 +0000269#ifdef CONFIG_A4M2K
270#define CONFIG_SYS_CS3_SIZE 0x00100000
271#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200272#define CONFIG_SYS_CS3_SIZE 0x00080000
Stefan Roesed4451d32013-02-07 02:10:11 +0000273#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200274/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
275#define CONFIG_SYS_CS3_CFG 0x0032B900
276
Stefan Roesed4451d32013-02-07 02:10:11 +0000277#ifndef CONFIG_A4M2K
Stefan Roese13b4f632012-08-14 15:04:19 +0200278/* Diagnosis Interface - see ticket #63 */
279#define CONFIG_SYS_CS4_START 0xEA000000
280#define CONFIG_SYS_CS4_SIZE 0x00000001
281/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
282#define CONFIG_SYS_CS4_CFG 0x0002B900
Stefan Roesed4451d32013-02-07 02:10:11 +0000283#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200284
Stefan Roesed4451d32013-02-07 02:10:11 +0000285/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
Stefan Roese13b4f632012-08-14 15:04:19 +0200286#define CONFIG_SYS_CS5_START 0xE8000000
Stefan Roesed4451d32013-02-07 02:10:11 +0000287#ifdef CONFIG_A4M2K
288#define CONFIG_SYS_CS5_SIZE 0x00100000
289#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200290#define CONFIG_SYS_CS5_SIZE 0x00010000
Stefan Roesed4451d32013-02-07 02:10:11 +0000291#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200292/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
293#define CONFIG_SYS_CS5_CFG 0x0032B900
294
295#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
296#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
Stefan Roesed4451d32013-02-07 02:10:11 +0000297#define CONFIG_SYS_CS1_CFG 0x0008FD00
Stefan Roese13b4f632012-08-14 15:04:19 +0200298#define CONFIG_SYS_CS2_CFG 0x0006F90C
299#else /* for pci_clk = 33 MHz */
300#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
301#define CONFIG_SYS_CS1_CFG 0x0001FB00
302#define CONFIG_SYS_CS2_CFG 0x0002F90C
303#endif
304
305#define CONFIG_SYS_CS_BURST 0x00000000
306/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
307/* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
308/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
309#define CONFIG_SYS_CS_DEADCYCLE 0x33030000
310
311#define CONFIG_SYS_RESET_ADDRESS 0xff000000
312
313/*
314 * Environment Configuration
315 */
316
Stefan Roese13b4f632012-08-14 15:04:19 +0200317#undef CONFIG_BOOTARGS
Stefan Roese13b4f632012-08-14 15:04:19 +0200318
Stefan Roese8aa34492013-04-25 23:20:23 +0000319#define CONFIG_SYS_AUTOLOAD "n"
320
Stefan Roese13b4f632012-08-14 15:04:19 +0200321#define CONFIG_PREBOOT "echo;" \
322 "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
323 "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
324 "echo"
325
326#undef CONFIG_BOOTARGS
327
Stefan Roese8aa34492013-04-25 23:20:23 +0000328#define CONFIG_SYS_FDT_BASE 0xfc1e0000
Mike Looijmans5aa79f22016-07-26 07:34:07 +0200329#define CONFIG_SYS_FDT_SIZE (16<<10)
Stefan Roese13b4f632012-08-14 15:04:19 +0200330
Stefan Roese13b4f632012-08-14 15:04:19 +0200331#define CONFIG_EXTRA_ENV_SETTINGS \
332 "netdev=eth0\0" \
333 "verify=no\0" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000334 "loadaddr=200000\0" \
335 "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
336 "kernel_addr_r=1000000\0" \
337 "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
338 "fdt_addr_r=1800000\0" \
339 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
340 "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
341 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
342 "rootpath=/opt/eldk-5.2.1/powerpc/" \
343 "core-image-minimal-mtdutils-dropbear-generic\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200344 "consoledev=ttyPSC0\0" \
345 "nfsargs=setenv bootargs root=/dev/nfs rw " \
346 "nfsroot=${serverip}:${rootpath}\0" \
347 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200348 "mtdargs=setenv bootargs root=/dev/mtdblock8 " \
Stefan Roese8aa34492013-04-25 23:20:23 +0000349 "rootfstype=squashfs,jffs2\0" \
350 "addhost=setenv bootargs ${bootargs} " \
351 "hostname=${hostname}\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200352 "addip=setenv bootargs ${bootargs} " \
353 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
354 ":${hostname}:${netdev}:off panic=1\0" \
355 "addtty=setenv bootargs ${bootargs} " \
356 "console=${consoledev},${baudrate}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200357 "flash_nfs=run nfsargs addip addtty addmtd addhost;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000358 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200359 "flash_mtd=run mtdargs addip addtty addmtd addhost;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000360 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200361 "flash_self=run ramargs addip addtty addmtd addhost;" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000362 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
363 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
364 "tftp ${fdt_addr_r} ${fdtfile};" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200365 "run nfsargs addip addtty addmtd addhost;" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000366 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
367 "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
368 "/u-boot-img.bin\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200369 "update=protect off fc000000 fc07ffff;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000370 "era fc000000 fc07ffff;" \
371 "cp.b ${loadaddr} fc000000 ${filesize}\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200372 "upd=run load;run update\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200373 "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
374 "run mtdargs addip addtty addmtd addhost;" \
375 "fdt addr 1800000;fdt boardsetup;fdt chosen;" \
376 "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
377 "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
378 "erase fc200000 fc6fffff;" \
379 "cp.b 1000000 fc200000 ${filesize}" \
380 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
381 "mtdids=" MTDIDS_DEFAULT "\0" \
382 "mtdparts=" MTDPARTS_DEFAULT "\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200383 ""
384
385#define CONFIG_BOOTCOMMAND "run flash_mtd"
386
387/*
388 * SPL related defines
389 */
Stefan Roese13b4f632012-08-14 15:04:19 +0200390#define CONFIG_SPL_FRAMEWORK
Stefan Roesed4451d32013-02-07 02:10:11 +0000391#define CONFIG_SPL_BOARD_INIT
Stefan Roese13b4f632012-08-14 15:04:19 +0200392#define CONFIG_SPL_TEXT_BASE 0xfc000000
Stefan Roese13b4f632012-08-14 15:04:19 +0200393
394/* Place BSS for SPL near end of SDRAM */
395#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
396#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
397
Stefan Roese13b4f632012-08-14 15:04:19 +0200398/* Place patched DT blob (fdt) at this address */
399#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
400
401/* Settings for real U-Boot to be loaded from NOR flash */
402#ifndef __ASSEMBLY__
403extern char __spl_flash_end[];
404#endif
405#define CONFIG_SYS_UBOOT_BASE __spl_flash_end
406#define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
407#define CONFIG_SYS_UBOOT_START 0x1000100
408
409#endif /* __CONFIG_H */