blob: 319983c4829bb9fbbac6f50abbd7bdd0571e7bb3 [file] [log] [blame]
Thomas Chouc960b132010-04-20 12:49:52 +08001/*
2 * Altera 10/100/1000 triple speed ethernet mac driver
3 *
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
Thomas Chouc960b132010-04-20 12:49:52 +080011#include <common.h>
Thomas Chou96fa1e42015-10-22 15:29:11 +080012#include <dm.h>
13#include <errno.h>
14#include <fdt_support.h>
15#include <memalign.h>
16#include <miiphy.h>
Thomas Chouc960b132010-04-20 12:49:52 +080017#include <net.h>
Thomas Chouc960b132010-04-20 12:49:52 +080018#include <asm/cache.h>
19#include <asm/dma-mapping.h>
Thomas Chou96fa1e42015-10-22 15:29:11 +080020#include <asm/io.h>
Thomas Chouc960b132010-04-20 12:49:52 +080021#include "altera_tse.h"
22
Thomas Chou96fa1e42015-10-22 15:29:11 +080023DECLARE_GLOBAL_DATA_PTR;
Thomas Chouc960b132010-04-20 12:49:52 +080024
Thomas Chou96fa1e42015-10-22 15:29:11 +080025static inline void alt_sgdma_construct_descriptor(
26 struct alt_sgdma_descriptor *desc,
27 struct alt_sgdma_descriptor *next,
28 void *read_addr,
29 void *write_addr,
Thomas Chouc960b132010-04-20 12:49:52 +080030 unsigned short length_or_eop,
31 int generate_eop,
32 int read_fixed,
Thomas Chou96fa1e42015-10-22 15:29:11 +080033 int write_fixed_or_sop)
Thomas Chouc960b132010-04-20 12:49:52 +080034{
Thomas Chou96fa1e42015-10-22 15:29:11 +080035 unsigned char val;
36
Thomas Chouc960b132010-04-20 12:49:52 +080037 /*
38 * Mark the "next" descriptor as "not" owned by hardware. This prevents
Thomas Chou96fa1e42015-10-22 15:29:11 +080039 * The SGDMA controller from continuing to process the chain.
Thomas Chouc960b132010-04-20 12:49:52 +080040 */
Thomas Chou96fa1e42015-10-22 15:29:11 +080041 next->descriptor_control = next->descriptor_control &
42 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
Thomas Chouc960b132010-04-20 12:49:52 +080043
Thomas Chou96fa1e42015-10-22 15:29:11 +080044 memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
45 desc->source = virt_to_phys(read_addr);
46 desc->destination = virt_to_phys(write_addr);
47 desc->next = virt_to_phys(next);
Thomas Chouc960b132010-04-20 12:49:52 +080048 desc->bytes_to_transfer = length_or_eop;
Thomas Chouc960b132010-04-20 12:49:52 +080049
50 /*
51 * Set the descriptor control block as follows:
52 * - Set "owned by hardware" bit
53 * - Optionally set "generate EOP" bit
54 * - Optionally set the "read from fixed address" bit
55 * - Optionally set the "write to fixed address bit (which serves
56 * serves as a "generate SOP" control bit in memory-to-stream mode).
57 * - Set the 4-bit atlantic channel, if specified
58 *
59 * Note this step is performed after all other descriptor information
60 * has been filled out so that, if the controller already happens to be
61 * pointing at this descriptor, it will not run (via the "owned by
62 * hardware" bit) until all other descriptor has been set up.
63 */
Thomas Chou96fa1e42015-10-22 15:29:11 +080064 val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
65 if (generate_eop)
66 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
67 if (read_fixed)
68 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
69 if (write_fixed_or_sop)
70 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
71 desc->descriptor_control = val;
Thomas Chouc960b132010-04-20 12:49:52 +080072}
73
Thomas Chou96fa1e42015-10-22 15:29:11 +080074static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
Thomas Chouc960b132010-04-20 12:49:52 +080075{
Thomas Chou96fa1e42015-10-22 15:29:11 +080076 int status;
77 ulong ctime;
Thomas Chouc960b132010-04-20 12:49:52 +080078
79 /* Wait for the descriptor (chain) to complete */
Thomas Chou96fa1e42015-10-22 15:29:11 +080080 ctime = get_timer(0);
81 while (1) {
82 status = readl(&regs->status);
83 if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
Thomas Chouc960b132010-04-20 12:49:52 +080084 break;
Thomas Chou96fa1e42015-10-22 15:29:11 +080085 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
86 status = -ETIMEDOUT;
87 debug("sgdma timeout\n");
88 break;
89 }
Thomas Chouc960b132010-04-20 12:49:52 +080090 }
91
Thomas Chou96fa1e42015-10-22 15:29:11 +080092 /* Clear Run */
93 writel(0, &regs->control);
94 /* Clear status */
95 writel(0xff, &regs->status);
Thomas Chouc960b132010-04-20 12:49:52 +080096
Thomas Chou96fa1e42015-10-22 15:29:11 +080097 return status;
98}
Joachim Foerster337aff52011-10-25 22:39:54 +000099
Thomas Chou96fa1e42015-10-22 15:29:11 +0800100static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
101 struct alt_sgdma_descriptor *desc)
102{
103 unsigned int val;
Thomas Chouc960b132010-04-20 12:49:52 +0800104
105 /* Point the controller at the descriptor */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800106 writel(virt_to_phys(desc), &regs->next_descriptor_pointer);
Thomas Chouc960b132010-04-20 12:49:52 +0800107
108 /*
109 * Set up SGDMA controller to:
110 * - Disable interrupt generation
111 * - Run once a valid descriptor is written to controller
112 * - Stop on an error with any particular descriptor
113 */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800114 val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
115 writel(val, &regs->control);
Thomas Chouc960b132010-04-20 12:49:52 +0800116
Thomas Chouc960b132010-04-20 12:49:52 +0800117 return 0;
118}
119
Thomas Chou96fa1e42015-10-22 15:29:11 +0800120static void tse_adjust_link(struct altera_tse_priv *priv,
121 struct phy_device *phydev)
Thomas Chouc960b132010-04-20 12:49:52 +0800122{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800123 struct alt_tse_mac *mac_dev = priv->mac_dev;
Thomas Chouc960b132010-04-20 12:49:52 +0800124 unsigned int refvar;
125
Thomas Chou96fa1e42015-10-22 15:29:11 +0800126 if (!phydev->link) {
127 debug("%s: No link.\n", phydev->dev->name);
128 return;
129 }
Thomas Chouc960b132010-04-20 12:49:52 +0800130
Thomas Chou96fa1e42015-10-22 15:29:11 +0800131 refvar = readl(&mac_dev->command_config);
132
133 if (phydev->duplex)
Thomas Chouc960b132010-04-20 12:49:52 +0800134 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
135 else
136 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
137
Thomas Chou96fa1e42015-10-22 15:29:11 +0800138 switch (phydev->speed) {
Thomas Chouc960b132010-04-20 12:49:52 +0800139 case 1000:
140 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
141 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
142 break;
143 case 100:
144 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
145 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
146 break;
147 case 10:
148 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
149 refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
150 break;
151 }
Thomas Chou96fa1e42015-10-22 15:29:11 +0800152 writel(refvar, &mac_dev->command_config);
Thomas Chouc960b132010-04-20 12:49:52 +0800153}
154
Thomas Chou96fa1e42015-10-22 15:29:11 +0800155static int altera_tse_send(struct udevice *dev, void *packet, int length)
Thomas Chouc960b132010-04-20 12:49:52 +0800156{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800157 struct altera_tse_priv *priv = dev_get_priv(dev);
158 struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
159 unsigned long tx_buf = (unsigned long)packet;
Thomas Chouc960b132010-04-20 12:49:52 +0800160
Thomas Chou96fa1e42015-10-22 15:29:11 +0800161 flush_dcache_range(tx_buf, tx_buf + length);
162 alt_sgdma_construct_descriptor(
163 tx_desc,
164 tx_desc + 1,
165 packet, /* read addr */
166 NULL, /* write addr */
Thomas Chouc960b132010-04-20 12:49:52 +0800167 length, /* length or EOP ,will change for each tx */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800168 1, /* gen eop */
169 0, /* read fixed */
170 1 /* write fixed or sop */
Thomas Chouc960b132010-04-20 12:49:52 +0800171 );
Thomas Chouc960b132010-04-20 12:49:52 +0800172
173 /* send the packet */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800174 alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
175 alt_sgdma_wait_transfer(priv->sgdma_tx);
176 debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
177
178 return tx_desc->actual_bytes_transferred;
Thomas Chouc960b132010-04-20 12:49:52 +0800179}
180
Thomas Chou96fa1e42015-10-22 15:29:11 +0800181static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
Thomas Chouc960b132010-04-20 12:49:52 +0800182{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800183 struct altera_tse_priv *priv = dev_get_priv(dev);
184 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
185 int packet_length;
Thomas Chouc960b132010-04-20 12:49:52 +0800186
Thomas Chou96fa1e42015-10-22 15:29:11 +0800187 if (rx_desc->descriptor_status &
Thomas Chouc960b132010-04-20 12:49:52 +0800188 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
Thomas Chouc960b132010-04-20 12:49:52 +0800189 packet_length = rx_desc->actual_bytes_transferred;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800190 debug("recv %d bytes\n", packet_length);
191 *packetp = priv->rx_buf;
Joachim Foerster70d52f92011-10-17 05:24:46 +0000192
193 return packet_length;
Thomas Chouc960b132010-04-20 12:49:52 +0800194 }
195
Thomas Chou96fa1e42015-10-22 15:29:11 +0800196 return -EAGAIN;
Thomas Chouc960b132010-04-20 12:49:52 +0800197}
198
Thomas Chou96fa1e42015-10-22 15:29:11 +0800199static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
200 int length)
Thomas Chouc960b132010-04-20 12:49:52 +0800201{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800202 struct altera_tse_priv *priv = dev_get_priv(dev);
203 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
204 unsigned long rx_buf = (unsigned long)priv->rx_buf;
205
206 alt_sgdma_wait_transfer(priv->sgdma_rx);
207 invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
208 alt_sgdma_construct_descriptor(
209 rx_desc,
210 rx_desc + 1,
211 NULL, /* read addr */
212 priv->rx_buf, /* write addr */
213 0, /* length or EOP */
214 0, /* gen eop */
215 0, /* read fixed */
216 0 /* write fixed or sop */
217 );
218
219 /* setup the sgdma */
220 alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
221 debug("recv setup\n");
222
223 return 0;
Thomas Chouc960b132010-04-20 12:49:52 +0800224}
225
Thomas Chou96fa1e42015-10-22 15:29:11 +0800226static void altera_tse_stop(struct udevice *dev)
Thomas Chouc960b132010-04-20 12:49:52 +0800227{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800228 struct altera_tse_priv *priv = dev_get_priv(dev);
229 struct alt_tse_mac *mac_dev = priv->mac_dev;
230 struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
231 struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
232 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
233 unsigned int status;
234 int ret;
235 ulong ctime;
Thomas Chouc960b132010-04-20 12:49:52 +0800236
237 /* clear rx desc & wait for sgdma to complete */
238 rx_desc->descriptor_control = 0;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800239 writel(0, &rx_sgdma->control);
240 ret = alt_sgdma_wait_transfer(rx_sgdma);
241 if (ret == -ETIMEDOUT)
242 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
243 &rx_sgdma->control);
Thomas Chouc960b132010-04-20 12:49:52 +0800244
Thomas Chou96fa1e42015-10-22 15:29:11 +0800245 writel(0, &tx_sgdma->control);
246 ret = alt_sgdma_wait_transfer(tx_sgdma);
247 if (ret == -ETIMEDOUT)
248 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
249 &tx_sgdma->control);
Thomas Chouc960b132010-04-20 12:49:52 +0800250
Thomas Chouc960b132010-04-20 12:49:52 +0800251 /* reset the mac */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800252 writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
253 ctime = get_timer(0);
254 while (1) {
255 status = readl(&mac_dev->command_config);
256 if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
Thomas Chouc960b132010-04-20 12:49:52 +0800257 break;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800258 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
259 debug("Reset mac timeout\n");
Thomas Chouc960b132010-04-20 12:49:52 +0800260 break;
261 }
262 }
Thomas Chouc960b132010-04-20 12:49:52 +0800263}
264
Thomas Chou96fa1e42015-10-22 15:29:11 +0800265static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
Thomas Chouc960b132010-04-20 12:49:52 +0800266{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800267 struct altera_tse_priv *priv = bus->priv;
268 struct alt_tse_mac *mac_dev = priv->mac_dev;
269 unsigned int value;
Thomas Chouc960b132010-04-20 12:49:52 +0800270
Thomas Chou96fa1e42015-10-22 15:29:11 +0800271 /* set mdio address */
272 writel(addr, &mac_dev->mdio_phy1_addr);
273 /* get the data */
274 value = readl(&mac_dev->mdio_phy1[reg]);
Thomas Chouc960b132010-04-20 12:49:52 +0800275
Thomas Chou96fa1e42015-10-22 15:29:11 +0800276 return value & 0xffff;
Thomas Chouc960b132010-04-20 12:49:52 +0800277}
278
Thomas Chou96fa1e42015-10-22 15:29:11 +0800279static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
280 u16 val)
Thomas Chouc960b132010-04-20 12:49:52 +0800281{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800282 struct altera_tse_priv *priv = bus->priv;
283 struct alt_tse_mac *mac_dev = priv->mac_dev;
Thomas Chouc960b132010-04-20 12:49:52 +0800284
Thomas Chou96fa1e42015-10-22 15:29:11 +0800285 /* set mdio address */
286 writel(addr, &mac_dev->mdio_phy1_addr);
287 /* set the data */
288 writel(val, &mac_dev->mdio_phy1[reg]);
Thomas Chouc960b132010-04-20 12:49:52 +0800289
Thomas Chou6c7c4442010-04-27 20:15:10 +0800290 return 0;
291}
292
Thomas Chou96fa1e42015-10-22 15:29:11 +0800293static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
Thomas Chouc960b132010-04-20 12:49:52 +0800294{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800295 struct mii_dev *bus = mdio_alloc();
Thomas Chouc960b132010-04-20 12:49:52 +0800296
Thomas Chou96fa1e42015-10-22 15:29:11 +0800297 if (!bus) {
298 printf("Failed to allocate MDIO bus\n");
299 return -ENOMEM;
300 }
Thomas Chouc960b132010-04-20 12:49:52 +0800301
Thomas Chou96fa1e42015-10-22 15:29:11 +0800302 bus->read = tse_mdio_read;
303 bus->write = tse_mdio_write;
304 snprintf(bus->name, sizeof(bus->name), name);
305
306 bus->priv = (void *)priv;
307
308 return mdio_register(bus);
309}
310
311static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
312{
313 struct phy_device *phydev;
314 unsigned int mask = 0xffffffff;
315
316 if (priv->phyaddr)
317 mask = 1 << priv->phyaddr;
318
319 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
320 if (!phydev)
321 return -ENODEV;
322
323 phy_connect_dev(phydev, dev);
324
325 phydev->supported &= PHY_GBIT_FEATURES;
326 phydev->advertising = phydev->supported;
327
328 priv->phydev = phydev;
329 phy_config(phydev);
330
331 return 0;
332}
333
334static int altera_tse_write_hwaddr(struct udevice *dev)
335{
336 struct altera_tse_priv *priv = dev_get_priv(dev);
337 struct alt_tse_mac *mac_dev = priv->mac_dev;
338 struct eth_pdata *pdata = dev_get_platdata(dev);
339 u8 *hwaddr = pdata->enetaddr;
340 unsigned int mac_lo, mac_hi;
341
342 mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
343 (hwaddr[1] << 8) | hwaddr[0];
344 mac_hi = (hwaddr[5] << 8) | hwaddr[4];
345 debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
346
347 writel(mac_lo, &mac_dev->mac_addr_0);
348 writel(mac_hi, &mac_dev->mac_addr_1);
349 writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
350 writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
351 writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
352 writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
353 writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
354 writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
355 writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
356 writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
357
358 return 0;
359}
360
361static int altera_tse_start(struct udevice *dev)
362{
363 struct altera_tse_priv *priv = dev_get_priv(dev);
364 struct alt_tse_mac *mac_dev = priv->mac_dev;
365 unsigned int val;
366 int ret;
Thomas Chouc960b132010-04-20 12:49:52 +0800367
368 /* need to create sgdma */
Thomas Chouc960b132010-04-20 12:49:52 +0800369 debug("Configuring rx desc\n");
Thomas Chou96fa1e42015-10-22 15:29:11 +0800370 altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
Thomas Chouc960b132010-04-20 12:49:52 +0800371 /* start TSE */
372 debug("Configuring TSE Mac\n");
373 /* Initialize MAC registers */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800374 writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
375 writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
376 writel(0, &mac_dev->rx_sel_full_threshold);
377 writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
378 writel(0, &mac_dev->tx_sel_full_threshold);
379 writel(8, &mac_dev->rx_almost_empty_threshold);
380 writel(8, &mac_dev->rx_almost_full_threshold);
381 writel(8, &mac_dev->tx_almost_empty_threshold);
382 writel(3, &mac_dev->tx_almost_full_threshold);
Thomas Chouc960b132010-04-20 12:49:52 +0800383
384 /* NO Shift */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800385 writel(0, &mac_dev->rx_cmd_stat);
386 writel(0, &mac_dev->tx_cmd_stat);
Thomas Chouc960b132010-04-20 12:49:52 +0800387
388 /* enable MAC */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800389 val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
390 writel(val, &mac_dev->command_config);
Thomas Chouc960b132010-04-20 12:49:52 +0800391
Thomas Chou96fa1e42015-10-22 15:29:11 +0800392 /* Start up the PHY */
393 ret = phy_startup(priv->phydev);
394 if (ret) {
395 debug("Could not initialize PHY %s\n",
396 priv->phydev->dev->name);
397 return ret;
Thomas Chouc960b132010-04-20 12:49:52 +0800398 }
399
Thomas Chou96fa1e42015-10-22 15:29:11 +0800400 tse_adjust_link(priv, priv->phydev);
401
402 if (!priv->phydev->link)
403 return -EIO;
404
405 return 0;
Thomas Chouc960b132010-04-20 12:49:52 +0800406}
407
Thomas Chou96fa1e42015-10-22 15:29:11 +0800408static int altera_tse_probe(struct udevice *dev)
Thomas Chouc960b132010-04-20 12:49:52 +0800409{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800410 struct eth_pdata *pdata = dev_get_platdata(dev);
411 struct altera_tse_priv *priv = dev_get_priv(dev);
412 const void *blob = gd->fdt_blob;
413 int node = dev->of_offset;
414 const char *list, *end;
415 const fdt32_t *cell;
416 void *base, *desc_mem = NULL;
417 unsigned long addr, size;
418 int len, idx;
419 int ret;
Thomas Chouc960b132010-04-20 12:49:52 +0800420
Thomas Chou96fa1e42015-10-22 15:29:11 +0800421 /*
422 * decode regs, assume address-cells and size-cells are both one.
423 * there are multiple reg tuples, and they need to match with
424 * reg-names.
425 */
426 list = fdt_getprop(blob, node, "reg-names", &len);
427 if (!list)
428 return -ENOENT;
429 end = list + len;
430 cell = fdt_getprop(blob, node, "reg", &len);
431 if (!cell)
432 return -ENOENT;
433 idx = 0;
434 while (list < end) {
435 addr = fdt_translate_address((void *)blob,
436 node, cell + idx);
437 size = fdt_addr_to_cpu(cell[idx + 1]);
438 base = ioremap(addr, size);
439 len = strlen(list);
440 if (strcmp(list, "control_port") == 0)
441 priv->mac_dev = base;
442 else if (strcmp(list, "rx_csr") == 0)
443 priv->sgdma_rx = base;
444 else if (strcmp(list, "tx_csr") == 0)
445 priv->sgdma_tx = base;
446 else if (strcmp(list, "s1") == 0)
447 desc_mem = base;
448 idx += 2;
449 list += (len + 1);
Thomas Chouc960b132010-04-20 12:49:52 +0800450 }
Thomas Chou96fa1e42015-10-22 15:29:11 +0800451 /* decode fifo depth */
452 priv->rx_fifo_depth = fdtdec_get_int(blob, node,
453 "rx-fifo-depth", 0);
454 priv->tx_fifo_depth = fdtdec_get_int(blob, node,
455 "tx-fifo-depth", 0);
456 /* decode phy */
457 addr = fdtdec_get_int(blob, node,
458 "phy-handle", 0);
459 addr = fdt_node_offset_by_phandle(blob, addr);
460 priv->phyaddr = fdtdec_get_int(blob, addr,
461 "reg", 0);
462 /* init desc */
463 len = sizeof(struct alt_sgdma_descriptor) * 4;
464 if (!desc_mem) {
465 desc_mem = dma_alloc_coherent(len, &addr);
466 if (!desc_mem)
467 return -ENOMEM;
Joachim Foersterb962ac72011-10-17 05:24:44 +0000468 }
Thomas Chou96fa1e42015-10-22 15:29:11 +0800469 memset(desc_mem, 0, len);
470 priv->tx_desc = desc_mem;
471 priv->rx_desc = priv->tx_desc + 2;
472 /* allocate recv packet buffer */
473 priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
474 if (!priv->rx_buf)
475 return -ENOMEM;
Joachim Foersterb962ac72011-10-17 05:24:44 +0000476
Thomas Chou96fa1e42015-10-22 15:29:11 +0800477 /* stop controller */
478 debug("Reset TSE & SGDMAs\n");
479 altera_tse_stop(dev);
Thomas Chouc960b132010-04-20 12:49:52 +0800480
Thomas Chou96fa1e42015-10-22 15:29:11 +0800481 /* start the phy */
482 priv->interface = pdata->phy_interface;
483 tse_mdio_init(dev->name, priv);
484 priv->bus = miiphy_get_dev_by_name(dev->name);
Thomas Chouc960b132010-04-20 12:49:52 +0800485
Thomas Chou96fa1e42015-10-22 15:29:11 +0800486 ret = tse_phy_init(priv, dev);
Thomas Chouc960b132010-04-20 12:49:52 +0800487
Thomas Chou96fa1e42015-10-22 15:29:11 +0800488 return ret;
Thomas Chouc960b132010-04-20 12:49:52 +0800489}
Thomas Chou96fa1e42015-10-22 15:29:11 +0800490
491static int altera_tse_ofdata_to_platdata(struct udevice *dev)
492{
493 struct eth_pdata *pdata = dev_get_platdata(dev);
494 const char *phy_mode;
495
496 pdata->phy_interface = -1;
497 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
498 if (phy_mode)
499 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
500 if (pdata->phy_interface == -1) {
501 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
502 return -EINVAL;
503 }
504
505 return 0;
506}
507
508static const struct eth_ops altera_tse_ops = {
509 .start = altera_tse_start,
510 .send = altera_tse_send,
511 .recv = altera_tse_recv,
512 .free_pkt = altera_tse_free_pkt,
513 .stop = altera_tse_stop,
514 .write_hwaddr = altera_tse_write_hwaddr,
515};
516
517static const struct udevice_id altera_tse_ids[] = {
518 { .compatible = "altr,tse-1.0", },
519 { }
520};
521
522U_BOOT_DRIVER(altera_tse) = {
523 .name = "altera_tse",
524 .id = UCLASS_ETH,
525 .of_match = altera_tse_ids,
526 .ops = &altera_tse_ops,
527 .ofdata_to_platdata = altera_tse_ofdata_to_platdata,
528 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
529 .priv_auto_alloc_size = sizeof(struct altera_tse_priv),
530 .probe = altera_tse_probe,
531};