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wdenk466b7412004-07-10 22:35:59 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Configuration settings for the sbc8240 board.
26 */
27
28/* ------------------------------------------------------------------------- */
29
30/*
31 * board/config.h - configuration options, board specific
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41
42#define CONFIG_MPC824X 1
43#define CONFIG_MPC8240 1
44#define CONFIG_WRSBC8240 1
45
46#define CONFIG_CONS_INDEX 1
47#define CONFIG_BAUDRATE 9600
48#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
49
50#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo"
51
52#undef CONFIG_BOOTARGS
53
54#define CONFIG_BOOTCOMMAND "version;echo;tftpboot $loadaddr $loadfile;bootvx" /* autoboot command */
55
56#define CONFIG_EXTRA_ENV_SETTINGS \
57 "bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st " \
58 "e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 " \
59 "tn=sbc8240 o=fei \0" \
60 "env_startaddr=FFF70000\0" \
61 "env_endaddr=FFF7FFFF\0" \
62 "loadfile=vxWorks.st\0" \
63 "loadaddr=0x01000000\0" \
64 "net_load=tftpboot $loadaddr $loadfile\0" \
65 "uboot_startaddr=FFF00000\0" \
66 "uboot_endaddr=FFF3FFFF\0" \
67 "update=tftp $loadaddr /u-boot.bin;" \
68 "protect off $uboot_startaddr $uboot_endaddr;" \
69 "era $uboot_startaddr $uboot_endaddr;" \
70 "cp.b $loadaddr $uboot_startaddr $filesize;" \
71 "protect on $uboot_startaddr $uboot_endaddr\0" \
72 "zapenv=protect off $env_startaddr $env_endaddr;" \
73 "era $env_startaddr $env_endaddr;" \
74 "protect on $env_startaddr $env_endaddr\0"
75
76#define CONFIG_BOOTDELAY 5
77
78#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
79
80#define CONFIG_ENV_OVERWRITE
81
82#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
83 CFG_CMD_BSP | \
84 CFG_CMD_DIAG | \
85 CFG_CMD_ELF | \
86 CFG_CMD_ENV | \
87 CFG_CMD_FLASH | \
88 CFG_CMD_PCI | \
89 CFG_CMD_PING | \
90 CFG_CMD_SDRAM | \
91 0 )
92
93/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
94 */
95#include <cmd_confdefs.h>
96
97/*
98 * Miscellaneous configurable options
99 */
100#define CFG_LONGHELP /* undef to save memory */
101#define CFG_PROMPT "=> " /* Monitor Command Prompt */
102#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
103
104#if 1
105#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
106#endif
107#ifdef CFG_HUSH_PARSER
108#define CFG_PROMPT_HUSH_PS2 "> "
109#endif
110
111#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
112#define CONFIG_IPADDR 192.168.193.102
113#define CONFIG_NETMASK 255.255.255.248
114#define CONFIG_SERVERIP 192.168.193.99
115
116#define CONFIG_STATUS_LED /* Status LED enabled */
117#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
118
119#define STATUS_LED_BIT 0x00000001
120#define STATUS_LED_PERIOD (CFG_HZ / 2)
121#define STATUS_LED_STATE STATUS_LED_BLINKING
122#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
123#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
124
125#ifndef __ASSEMBLY__
126/* LEDs */
127typedef unsigned int led_id_t;
128
129#define __led_toggle(_msk) \
130 do { \
131 *((volatile char *) (CFG_LED_BASE)) ^= (_msk); \
132 } while(0)
133
134#define __led_set(_msk, _st) \
135 do { \
136 if ((_st)) \
137 *((volatile char *) (CFG_LED_BASE)) |= (_msk); \
138 else \
139 *((volatile char *) (CFG_LED_BASE)) &= ~(_msk); \
140 } while(0)
141
142#define __led_init(msk, st) __led_set(msk, st)
143
144#endif
145
146#define CONFIG_MISC_INIT_R
147#define CFG_LED_BASE 0xFFE80000
148
149/* Print Buffer Size
150 */
151#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
152
153#define CFG_MAXARGS 16 /* max number of command args */
154#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
155#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
156
157/*-----------------------------------------------------------------------
158 * Start addresses for the final memory configuration
159 * (Set up by the startup code)
160 * Please note that CFG_SDRAM_BASE _must_ start at 0
161 */
162#define CFG_SDRAM_BASE 0x00000000
163#define CFG_FLASH_BASE 0xFFF00000
164
165#define CFG_RESET_ADDRESS 0xFFF00100
166
167#define CFG_EUMB_ADDR 0xFCE00000
168
169#define CFG_MONITOR_BASE TEXT_BASE
170
171#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
172#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
173
174#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
175#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
176
177 /* Maximum amount of RAM.
178 */
179#define CFG_MAX_RAM_SIZE 0x10000000
180
181#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
182#undef CFG_RAMBOOT
183#else
184#define CFG_RAMBOOT
185#endif
186
187/*-----------------------------------------------------------------------
188 * Definitions for initial stack pointer and data area
189 */
190
191 /* Size in bytes reserved for initial data
192 */
193#define CFG_GBL_DATA_SIZE 128
194
195#define CFG_INIT_RAM_ADDR 0x40000000
196#define CFG_INIT_RAM_END 0x1000
197#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
198
199/*
200 * NS16550 Configuration
201 */
202#define CFG_NS16550
203#define CFG_NS16550_SERIAL
204
205#define CFG_NS16550_REG_SIZE 1
206
207#define CFG_NS16550_CLK 3686400
208
209#define CFG_NS16550_COM1 0xFFF80000
210
211/*
212 * Low Level Configuration Settings
213 * (address mappings, register initial values, etc.)
214 * You should know what you are doing if you make changes here.
215 * For the detail description refer to the MPC8240 user's manual.
216 */
217
218#define CONFIG_SYS_CLK_FREQ 33000000
219#define CFG_HZ 1000
220#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
221
222 /* Bit-field values for MCCR1.
223 */
224#define CFG_ROMNAL 0
225#define CFG_ROMFAL 7
226
227 /* Bit-field values for MCCR2.
228 */
229#define CFG_REFINT 430 /* Refresh interval */
230
231 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
232 */
233#define CFG_BSTOPRE 192
234
235 /* Bit-field values for MCCR3.
236 */
237#define CFG_REFREC 2 /* Refresh to activate interval */
238#define CFG_RDLAT 3 /* Data latancy from read command */
239
240 /* Bit-field values for MCCR4.
241 */
242#define CFG_PRETOACT 2 /* Precharge to activate interval */
243#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
244#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
245#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
246#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
247#define CFG_ACTORW 2
248#define CFG_REGISTERD_TYPE_BUFFER 1
249
250/* Memory bank settings.
251 * Only bits 20-29 are actually used from these vales to set the
252 * start/end addresses. The upper two bits will always be 0, and the lower
253 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
254 * address. Refer to the MPC8240 book.
255 */
256
257#define CFG_BANK0_START 0x00000000
258#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
259#define CFG_BANK0_ENABLE 1
260#define CFG_BANK1_START 0x3ff00000
261#define CFG_BANK1_END 0x3fffffff
262#define CFG_BANK1_ENABLE 0
263#define CFG_BANK2_START 0x3ff00000
264#define CFG_BANK2_END 0x3fffffff
265#define CFG_BANK2_ENABLE 0
266#define CFG_BANK3_START 0x3ff00000
267#define CFG_BANK3_END 0x3fffffff
268#define CFG_BANK3_ENABLE 0
269#define CFG_BANK4_START 0x3ff00000
270#define CFG_BANK4_END 0x3fffffff
271#define CFG_BANK4_ENABLE 0
272#define CFG_BANK5_START 0x3ff00000
273#define CFG_BANK5_END 0x3fffffff
274#define CFG_BANK5_ENABLE 0
275#define CFG_BANK6_START 0x3ff00000
276#define CFG_BANK6_END 0x3fffffff
277#define CFG_BANK6_ENABLE 0
278#define CFG_BANK7_START 0x3ff00000
279#define CFG_BANK7_END 0x3fffffff
280#define CFG_BANK7_ENABLE 0
281
282#define CFG_ODCR 0xff
283
284#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
285#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
286
287#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
288#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
289
290#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
291#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
292
293#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
294#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
295
296#define CFG_DBAT0L CFG_IBAT0L
297#define CFG_DBAT0U CFG_IBAT0U
298#define CFG_DBAT1L CFG_IBAT1L
299#define CFG_DBAT1U CFG_IBAT1U
300#define CFG_DBAT2L CFG_IBAT2L
301#define CFG_DBAT2U CFG_IBAT2U
302#define CFG_DBAT3L CFG_IBAT3L
303#define CFG_DBAT3U CFG_IBAT3U
304
305/*
306 * For booting Linux, the board info and command line data
307 * have to be in the first 8 MB of memory, since this is
308 * the maximum mapped by the Linux kernel during initialization.
309 */
310#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
311
312/*-----------------------------------------------------------------------
313 * FLASH organization
314 */
315#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
316#define CFG_MAX_FLASH_SECT 256 /* Max number of sectors in one bank */
317
318#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
319#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
320
321/*
322 * Init Memory Controller:
323 *
324 * BR0/1 and OR0/1 (FLASH)
325 */
326
327#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
328#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
329
330 /* Warining: environment is not EMBEDDED in the U-Boot code.
331 * It's stored in flash separately.
332 */
333#define CFG_ENV_IS_IN_FLASH 1
334#define CFG_ENV_ADDR 0xFFF70000
335#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
336#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
337#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
338
339/*-----------------------------------------------------------------------
340 * Cache Configuration
341 */
342#define CFG_CACHELINE_SIZE 32
343#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
344# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
345#endif
346
347/*
348 * Internal Definitions
349 *
350 * Boot Flags
351 */
352#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
353#define BOOTFLAG_WARM 0x02 /* Software reboot */
354
355/*-----------------------------------------------------------------------
356 * PCI stuff
357 *-----------------------------------------------------------------------
358 */
359#define CONFIG_PCI /* include pci support */
360#define CONFIG_PCI_PNP /* we need Plug 'n Play */
361#define CONFIG_NET_MULTI /* Multi ethernet cards support */
362#define CONFIG_TULIP
363#define CONFIG_EEPRO100
364#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
365#endif /* __CONFIG_H */