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TsiChungLiewaa5f1f92008-01-14 17:23:08 -06001/*
2 * Configuation settings for the Freescale MCF5373 FireEngine board.
3 *
Alison Wang2ee03c62012-03-25 19:18:14 +00004 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiewaa5f1f92008-01-14 17:23:08 -06005 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiewaa5f1f92008-01-14 17:23:08 -06008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5373EVB_H
15#define _M5373EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060021
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060022#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_UART_PORT (0)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060024#define CONFIG_BAUDRATE 115200
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060025
26#undef CONFIG_WATCHDOG
27#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
28
29/* Command line configuration */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060030#define CONFIG_CMD_CACHE
31#define CONFIG_CMD_DATE
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060032#define CONFIG_CMD_I2C
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060033#define CONFIG_CMD_MII
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060034#define CONFIG_CMD_PING
35#define CONFIG_CMD_REGINFO
36
Alison Wang2ee03c62012-03-25 19:18:14 +000037#ifdef CONFIG_NANDFLASH_SIZE
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060038# define CONFIG_CMD_NAND
39#endif
40
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_UNIFY_CACHE
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060042
43#define CONFIG_MCFFEC
44#ifdef CONFIG_MCFFEC
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060045# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050046# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047# define CONFIG_SYS_DISCOVER_PHY
48# define CONFIG_SYS_RX_ETH_BUFFER 8
49# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060050
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051# define CONFIG_SYS_FEC0_PINMUX 0
52# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020053# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
55# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060056# define FECDUPLEX FULL
57# define FECSPEED _100BASET
58# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
60# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060061# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060063#endif
64
65#define CONFIG_MCFRTC
66#undef RTC_DEBUG
67
68/* Timer */
69#define CONFIG_MCFTMR
70#undef CONFIG_MCFPIT
71
72/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020073#define CONFIG_SYS_I2C
74#define CONFIG_SYS_I2C_FSL
75#define CONFIG_SYS_FSL_I2C_SPEED 80000
76#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
77#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060079
80#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
81#define CONFIG_UDP_CHECKSUM
82
83#ifdef CONFIG_MCFFEC
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060084# define CONFIG_IPADDR 192.162.1.2
85# define CONFIG_NETMASK 255.255.255.0
86# define CONFIG_SERVERIP 192.162.1.1
87# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060088#endif /* FEC_ENET */
89
90#define CONFIG_HOSTNAME M5373EVB
91#define CONFIG_EXTRA_ENV_SETTINGS \
92 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +020093 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060094 "u-boot=u-boot.bin\0" \
95 "load=tftp ${loadaddr) ${u-boot}\0" \
96 "upd=run load; run prog\0" \
Jason Jin09933fb2011-08-19 10:10:40 +080097 "prog=prot off 0 3ffff;" \
98 "era 0 3ffff;" \
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060099 "cp.b ${loadaddr} 0 ${filesize};" \
100 "save\0" \
101 ""
102
103#define CONFIG_PRAM 512 /* 512 KB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600105
106#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600108#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600110#endif
111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
113#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
114#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
115#define CONFIG_SYS_LOAD_ADDR 0x40010000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_CLK 80000000
118#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_MBAR 0xFC000000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600123
124/*
125 * Low Level Configuration Settings
126 * (address mappings, register initial values, etc.)
127 * You should know what you are doing if you make changes here.
128 */
129/*-----------------------------------------------------------------------
130 * Definitions for initial stack pointer and data area (in DPRAM)
131 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200133#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200135#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600137
138/*-----------------------------------------------------------------------
139 * Start addresses for the final memory configuration
140 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_SDRAM_BASE 0x40000000
144#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
145#define CONFIG_SYS_SDRAM_CFG1 0x53722730
146#define CONFIG_SYS_SDRAM_CFG2 0x56670000
147#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
148#define CONFIG_SYS_SDRAM_EMOD 0x40010000
149#define CONFIG_SYS_SDRAM_MODE 0x018D0000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
152#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
155#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
158#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600159
160/*
161 * For booting Linux, the board info and command line data
162 * have to be in the first 8 MB of memory, since this is
163 * the maximum mapped by the Linux kernel during initialization ??
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000166#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600167
168/*-----------------------------------------------------------------------
169 * FLASH organization
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_FLASH_CFI
172#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200173# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
175# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
176# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
177# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
178# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600179#endif
180
Alison Wang2ee03c62012-03-25 19:18:14 +0000181#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182# define CONFIG_SYS_MAX_NAND_DEVICE 1
183# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
184# define CONFIG_SYS_NAND_SIZE 1
185# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600186# define NAND_ALLOW_ERASE_ALL 1
187# define CONFIG_JFFS2_NAND 1
188# define CONFIG_JFFS2_DEV "nand0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600190# define CONFIG_JFFS2_PART_OFFSET 0x00000000
191#endif
192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600194
195/* Configuration for environment
196 * Environment is embedded in u-boot in the second sector of the flash
197 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200198#define CONFIG_ENV_OFFSET 0x4000
199#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200200#define CONFIG_ENV_IS_IN_FLASH 1
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600201
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200202#define LDS_BOARD_TEXT \
203 . = DEFINED(env_offset) ? env_offset : .; \
204 common/env_embedded.o (.text*);
205
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600206/*-----------------------------------------------------------------------
207 * Cache Configuration
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600210
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600211#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200212 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600213#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200214 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600215#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
216#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
217 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
218 CF_ACR_EN | CF_ACR_SM_ALL)
219#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
220 CF_CACR_DCM_P)
221
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600222/*-----------------------------------------------------------------------
223 * Chipselect bank definitions
224 */
225/*
226 * CS0 - NOR Flash 1, 2, 4, or 8MB
227 * CS1 - CompactFlash and registers
228 * CS2 - NAND Flash 16, 32, or 64MB
229 * CS3 - Available
230 * CS4 - Available
231 * CS5 - Available
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_CS0_BASE 0
234#define CONFIG_SYS_CS0_MASK 0x007f0001
235#define CONFIG_SYS_CS0_CTRL 0x00001fa0
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_CS1_BASE 0x10000000
238#define CONFIG_SYS_CS1_MASK 0x001f0001
239#define CONFIG_SYS_CS1_CTRL 0x002A3780
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600240
Alison Wang2ee03c62012-03-25 19:18:14 +0000241#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_CS2_BASE 0x20000000
Alison Wang2ee03c62012-03-25 19:18:14 +0000243#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_CS2_CTRL 0x00001f60
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600245#endif
246
247#endif /* _M5373EVB_H */