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Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00001/*
2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
3 *
Tom Rini0b179982013-07-24 09:34:30 -04004 * SPDX-License-Identifier: GPL-2.0
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00005 */
6
Paul Burton7a9d1092013-11-09 10:22:08 +00007#ifndef _MALTA_CONFIG_H
8#define _MALTA_CONFIG_H
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00009
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000010/*
11 * System configuration
12 */
Paul Burton7a9d1092013-11-09 10:22:08 +000013#define CONFIG_MALTA
Paul Burton5f978d72014-04-07 10:11:23 +010014#define CONFIG_BOARD_EARLY_INIT_F
15#define CONFIG_DISPLAY_BOARDINFO
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000016
Gabor Juhosab413052013-10-24 14:32:00 +020017#define CONFIG_MEMSIZE_IN_BYTES
18
Gabor Juhosfeaa6062013-05-22 03:57:42 +000019#define CONFIG_PCI
20#define CONFIG_PCI_GT64120
Paul Burtonbaf37f02013-11-08 11:18:50 +000021#define CONFIG_PCI_MSC01
Gabor Juhosfeaa6062013-05-22 03:57:42 +000022#define CONFIG_PCI_PNP
Gabor Juhosf1957492013-05-22 03:57:44 +000023#define CONFIG_PCNET
Paul Burtone0878af2013-11-08 11:18:52 +000024#define CONFIG_PCNET_79C973
25#define PCNET_HAS_PROM
Gabor Juhosfeaa6062013-05-22 03:57:42 +000026
Paul Burton3ced12a2013-11-08 11:18:55 +000027#define CONFIG_MISC_INIT_R
28#define CONFIG_RTC_MC146818
29#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
30
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000031/*
32 * CPU Configuration
33 */
34#define CONFIG_SYS_MHZ 250 /* arbitrary value */
35#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000036
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000037/*
38 * Memory map
39 */
Gabor Juhos10473d02013-11-12 16:47:32 +010040#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */
41#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000042
43#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
44#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
45
46#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
47
48#define CONFIG_SYS_LOAD_ADDR 0x81000000
49#define CONFIG_SYS_MEMTEST_START 0x80100000
50#define CONFIG_SYS_MEMTEST_END 0x80800000
51
52#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
53#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
Paul Burton67d47522013-11-26 17:45:28 +000054#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000055
56/*
57 * Console configuration
58 */
Nikita Kiryanov181bd9d2015-08-03 12:36:58 +030059#undef CONFIG_SYS_PROMPT
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000060#if defined(CONFIG_SYS_LITTLE_ENDIAN)
Paul Burton7a9d1092013-11-09 10:22:08 +000061#define CONFIG_SYS_PROMPT "maltael # "
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000062#else
Paul Burton7a9d1092013-11-09 10:22:08 +000063#define CONFIG_SYS_PROMPT "malta # "
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000064#endif
65
66#define CONFIG_SYS_CBSIZE 256
67#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
68 sizeof(CONFIG_SYS_PROMPT) + 16)
69#define CONFIG_SYS_MAXARGS 16
70
Paul Burtona3bdaac2015-01-29 10:38:22 +000071#define CONFIG_SYS_HUSH_PARSER
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000072#define CONFIG_AUTO_COMPLETE
73#define CONFIG_CMDLINE_EDITING
74
75/*
76 * Serial driver
77 */
78#define CONFIG_BAUDRATE 115200
79
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000080#define CONFIG_SYS_NS16550_SERIAL
81#define CONFIG_SYS_NS16550_REG_SIZE 1
Paul Burton72117da2013-11-26 17:45:26 +000082#define CONFIG_SYS_NS16550_CLK (115200 * 16)
Daniel Schwierzeck99511822016-01-09 17:32:44 +010083#define CONFIG_SYS_NS16550_COM1 0xb80003f8
84#define CONFIG_SYS_NS16550_COM2 0xbb0003f8
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000085#define CONFIG_CONS_INDEX 1
86
87/*
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000088 * Flash configuration
89 */
Daniel Schwierzeck99511822016-01-09 17:32:44 +010090#define CONFIG_SYS_FLASH_BASE 0xbe000000
Gabor Juhos52caee02013-05-22 03:57:39 +000091#define CONFIG_SYS_MAX_FLASH_BANKS 1
92#define CONFIG_SYS_MAX_FLASH_SECT 128
93#define CONFIG_SYS_FLASH_CFI
94#define CONFIG_FLASH_CFI_DRIVER
95#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000096
97/*
Paul Burtonfba6f452013-11-08 11:18:56 +000098 * Environment
99 */
100#define CONFIG_ENV_IS_IN_FLASH
101#define CONFIG_ENV_SECT_SIZE 0x20000
102#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
103#define CONFIG_ENV_ADDR \
104 (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
105
106/*
Paul Burtonba21a452015-01-29 10:38:20 +0000107 * IDE/ATA
108 */
109#define CONFIG_SYS_IDE_MAXBUS 1
110#define CONFIG_SYS_IDE_MAXDEVICE 2
111#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
112#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
113#define CONFIG_SYS_ATA_DATA_OFFSET 0
114#define CONFIG_SYS_ATA_REG_OFFSET 0
115
116/*
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +0000117 * Commands
118 */
Paul Burton3ced12a2013-11-08 11:18:55 +0000119#define CONFIG_CMD_DATE
Paul Burtone0878af2013-11-08 11:18:52 +0000120#define CONFIG_CMD_DHCP
Paul Burtonba21a452015-01-29 10:38:20 +0000121#define CONFIG_CMD_IDE
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000122#define CONFIG_CMD_PCI
Gabor Juhosf1957492013-05-22 03:57:44 +0000123#define CONFIG_CMD_PING
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000124
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +0000125#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */
126
Paul Burton7a9d1092013-11-09 10:22:08 +0000127#endif /* _MALTA_CONFIG_H */