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wdenk384ae022002-11-05 00:17:55 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenk384ae022002-11-05 00:17:55 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */
38
39#undef CONFIG_8xx_CONS_SMC1
40#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
41#undef CONFIG_8xx_CONS_NONE
42#define CONFIG_BAUDRATE 115200
43#if 0
44#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
45#else
46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47#endif
48#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */
49
wdenk384ae022002-11-05 00:17:55 +000050#define CONFIG_BOARD_TYPES 1 /* support board types */
51
52#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
53 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
54 "nfsaddrs=10.0.0.99:10.0.0.2"
55
56#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
57#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
58
59#undef CONFIG_WATCHDOG /* watchdog disabled */
60
61#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
62
63#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
64
65#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
66 CFG_CMD_ASKENV | \
wdenk414eec32005-04-02 22:37:54 +000067 CFG_CMD_DATE | \
wdenk384ae022002-11-05 00:17:55 +000068 CFG_CMD_DHCP | \
wdenk414eec32005-04-02 22:37:54 +000069 CFG_CMD_NFS | \
70 CFG_CMD_SNTP )
wdenk384ae022002-11-05 00:17:55 +000071
72/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
73#include <cmd_confdefs.h>
74
75/*
76 * Miscellaneous configurable options
77 */
78#define CFG_LONGHELP /* undef to save memory */
79#define CFG_PROMPT "=> " /* Monitor Command Prompt */
80#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
81#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
82#else
83#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
84#endif
85#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
86#define CFG_MAXARGS 16 /* max number of command args */
87#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
88
89#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
90#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
91
92#define CFG_LOAD_ADDR 0x100000 /* default load address */
93
94#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
95
96#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
97
98/*
99 * Low Level Configuration Settings
100 * (address mappings, register initial values, etc.)
101 * You should know what you are doing if you make changes here.
102 */
103/*-----------------------------------------------------------------------
104 * Internal Memory Mapped Register
105 */
106#define CFG_IMMR 0xFFF00000
107
108/*-----------------------------------------------------------------------
109 * Definitions for initial stack pointer and data area (in DPRAM)
110 */
111#define CFG_INIT_RAM_ADDR CFG_IMMR
112#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
113#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
114#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
115#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
116
117/*-----------------------------------------------------------------------
118 * Start addresses for the final memory configuration
119 * (Set up by the startup code)
120 * Please note that CFG_SDRAM_BASE _must_ start at 0
121 */
122#define CFG_SDRAM_BASE 0x00000000
123#define CFG_FLASH_BASE 0x40000000
124#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
125#define CFG_MONITOR_BASE CFG_FLASH_BASE
126#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
127
128/*
129 * For booting Linux, the board info and command line data
130 * have to be in the first 8 MB of memory, since this is
131 * the maximum mapped by the Linux kernel during initialization.
132 */
133#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
134
135/*-----------------------------------------------------------------------
136 * FLASH organization
137 */
138#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
139#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
140
141#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
142#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
143
144#define CFG_ENV_IS_IN_FLASH 1
145#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
146#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
147
148/* Address and size of Redundant Environment Sector */
149#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
150#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
151
152/*-----------------------------------------------------------------------
153 * Hardware Information Block
154 */
155#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
156#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
157#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
158
159/*-----------------------------------------------------------------------
160 * Cache Configuration
161 */
162#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
163#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
164#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
165#endif
166
167/*-----------------------------------------------------------------------
168 * SYPCR - System Protection Control 11-9
169 * SYPCR can only be written once after reset!
170 *-----------------------------------------------------------------------
171 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
172 */
173#if defined(CONFIG_WATCHDOG)
174#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
175 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
176#else
177#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
178#endif
179
180/*-----------------------------------------------------------------------
181 * SIUMCR - SIU Module Configuration 11-6
182 *-----------------------------------------------------------------------
183 * PCMCIA config., multi-function pin tri-state
184 */
185#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
186
187/*-----------------------------------------------------------------------
188 * TBSCR - Time Base Status and Control 11-26
189 *-----------------------------------------------------------------------
190 * Clear Reference Interrupt Status, Timebase freezing enabled
191 */
192#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
193
194/*-----------------------------------------------------------------------
195 * RTCSC - Real-Time Clock Status and Control Register 11-27
196 *-----------------------------------------------------------------------
197 */
198#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
199
200/*-----------------------------------------------------------------------
201 * PISCR - Periodic Interrupt Status and Control 11-31
202 *-----------------------------------------------------------------------
203 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
204 */
205#define CFG_PISCR (PISCR_PS | PISCR_PITF)
206
207/*-----------------------------------------------------------------------
208 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
209 *-----------------------------------------------------------------------
210 * Reset PLL lock status sticky bit, timer expired status bit and timer
211 * interrupt status bit - leave PLL multiplication factor unchanged !
212 */
213#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
214
215/*-----------------------------------------------------------------------
216 * SCCR - System Clock and reset Control Register 15-27
217 *-----------------------------------------------------------------------
218 * Set clock output, timebase and RTC source and divider,
219 * power management and some other internal clocks
220 */
221#define SCCR_MASK SCCR_EBDF11
222#define CFG_SCCR (SCCR_TBS | \
223 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
224 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
225 SCCR_DFALCD00)
226
227/*-----------------------------------------------------------------------
228 * PCMCIA stuff
229 *-----------------------------------------------------------------------
230 *
231 */
232#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
233#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
234#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
235#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
236#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
237#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
238#define CFG_PCMCIA_IO_ADDR (0xEC000000)
239#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
240
241/*-----------------------------------------------------------------------
242 *
243 *-----------------------------------------------------------------------
244 *
245 */
wdenk384ae022002-11-05 00:17:55 +0000246#define CFG_DER 0
247
248/*
249 * Init Memory Controller:
250 *
251 * BR0/1 and OR0/1 (FLASH)
252 */
253
254#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
255#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
256
257/* used to re-map FLASH both when starting from SRAM or FLASH:
258 * restrict access enough to keep SRAM working (if any)
259 * but not too much to meddle with FLASH accesses
260 */
261#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
262#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
263
264/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
265#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
266 OR_SCY_5_CLK | OR_EHTR)
267
268#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
269#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
270#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
271
272#define CFG_OR1_REMAP CFG_OR0_REMAP
273#define CFG_OR1_PRELIM CFG_OR0_PRELIM
274#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
275
276/*
277 * BR2/3 and OR2/3 (SDRAM)
278 *
279 */
280#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
281#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
282#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
283
284/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
285#define CFG_OR_TIMING_SDRAM 0x00000A00
286
287#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
288#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
289
290#define CFG_OR3_PRELIM CFG_OR2_PRELIM
291#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
292
293/*
294 * Memory Periodic Timer Prescaler
295 */
296
297/* periodic timer for refresh */
298#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
299
300/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
301#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
302#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
303
304/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
305#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
306#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
307
308/*
309 * MAMR settings for SDRAM
310 */
311
312/* 8 column SDRAM */
313#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
314 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
315 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
316/* 9 column SDRAM */
317#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
318 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
319 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
320
321
322/*
323 * Internal Definitions
324 *
325 * Boot Flags
326 */
327#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
328#define BOOTFLAG_WARM 0x02 /* Software reboot */
329
330#endif /* __CONFIG_H */