wdenk | 384cc68 | 2005-04-03 22:35:21 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004 Freescale Semiconductor. |
| 3 | * (C) Copyright 2002,2003 Motorola,Inc. |
| 4 | * Xianghua Xiao <X.Xiao@motorola.com> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | /* |
| 26 | * pm854 board configuration file |
| 27 | * |
| 28 | * Please refer to doc/README.mpc85xx for more info. |
| 29 | * |
| 30 | * Make sure you change the MAC address and other network params first, |
| 31 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. |
| 32 | */ |
| 33 | |
| 34 | #ifndef __CONFIG_H |
| 35 | #define __CONFIG_H |
| 36 | |
| 37 | /* High Level Configuration Options */ |
| 38 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 39 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 40 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ |
| 41 | #define CONFIG_MPC8540 1 /* MPC8540 specific */ |
| 42 | #define CONFIG_PM854 1 /* PM854 board specific */ |
| 43 | |
| 44 | #define CONFIG_PCI |
| 45 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 46 | #define CONFIG_ENV_OVERWRITE |
| 47 | #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/ |
| 48 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 49 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ |
| 50 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
| 51 | |
| 52 | |
| 53 | /* |
| 54 | * sysclk for MPC85xx |
| 55 | * |
| 56 | * Two valid values are: |
| 57 | * 33000000 |
| 58 | * 66000000 |
| 59 | * |
| 60 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz |
| 61 | * is likely the desired value here, so that is now the default. |
| 62 | * The board, however, can run at 66MHz. In any event, this value |
| 63 | * must match the settings of some switches. Details can be found |
| 64 | * in the README.mpc85xxads. |
| 65 | */ |
| 66 | |
| 67 | #ifndef CONFIG_SYS_CLK_FREQ |
| 68 | #define CONFIG_SYS_CLK_FREQ 66000000 |
| 69 | #endif |
| 70 | |
| 71 | |
| 72 | /* |
| 73 | * These can be toggled for performance analysis, otherwise use default. |
| 74 | */ |
| 75 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 76 | #define CONFIG_BTB /* toggle branch predition */ |
| 77 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
| 78 | |
| 79 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
| 80 | |
| 81 | #undef CFG_DRAM_TEST /* memory test, takes time */ |
| 82 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ |
| 83 | #define CFG_MEMTEST_END 0x00400000 |
| 84 | |
| 85 | |
| 86 | /* |
| 87 | * Base addresses -- Note these are effective addresses where the |
| 88 | * actual resources get mapped (not physical addresses) |
| 89 | */ |
| 90 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 91 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
| 92 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
| 93 | |
| 94 | |
| 95 | /* |
| 96 | * DDR Setup |
| 97 | */ |
| 98 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 99 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
| 100 | |
| 101 | #if defined(CONFIG_SPD_EEPROM) |
| 102 | /* |
| 103 | * Determine DDR configuration from I2C interface. |
| 104 | */ |
| 105 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
| 106 | |
| 107 | #else |
| 108 | /* |
| 109 | * Manually set up DDR parameters |
| 110 | */ |
| 111 | #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */ |
| 112 | #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ |
| 113 | #define CFG_DDR_CS0_CONFIG 0x80000102 |
| 114 | #define CFG_DDR_TIMING_1 0x47444321 |
| 115 | #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ |
| 116 | #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ |
| 117 | #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ |
| 118 | #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ |
| 119 | #endif |
| 120 | |
| 121 | |
| 122 | /* |
| 123 | * SDRAM on the Local Bus |
| 124 | */ |
| 125 | #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
| 126 | #define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ |
| 127 | |
| 128 | #define CFG_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */ |
| 129 | #define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */ |
| 130 | |
| 131 | #define CFG_OR0_PRELIM 0xfe006f67 /* 32 MB Flash */ |
| 132 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
| 133 | #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
| 134 | #undef CFG_FLASH_CHECKSUM |
| 135 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 136 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 137 | |
| 138 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 139 | |
| 140 | |
| 141 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
| 142 | #define CFG_RAMBOOT |
| 143 | #else |
| 144 | #undef CFG_RAMBOOT |
| 145 | #endif |
| 146 | |
wdenk | 384cc68 | 2005-04-03 22:35:21 +0000 | [diff] [blame] | 147 | /* |
| 148 | * Local Bus Definitions |
| 149 | */ |
wdenk | 384cc68 | 2005-04-03 22:35:21 +0000 | [diff] [blame] | 150 | #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
| 151 | #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ |
| 152 | #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| 153 | #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ |
wdenk | 8b0bfc6 | 2005-04-03 23:11:38 +0000 | [diff] [blame] | 154 | |
wdenk | 384cc68 | 2005-04-03 22:35:21 +0000 | [diff] [blame] | 155 | |
| 156 | #define CONFIG_L1_INIT_RAM |
| 157 | #define CFG_INIT_RAM_LOCK 1 |
| 158 | #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
| 159 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
| 160 | |
| 161 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 162 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 163 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 164 | |
| 165 | #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
| 166 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
| 167 | |
| 168 | /* Serial Port */ |
| 169 | #define CONFIG_CONS_INDEX 1 |
| 170 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 171 | #define CFG_NS16550 |
| 172 | #define CFG_NS16550_SERIAL |
| 173 | #define CFG_NS16550_REG_SIZE 1 |
| 174 | #define CFG_NS16550_CLK get_bus_freq(0) |
| 175 | |
| 176 | #define CFG_BAUDRATE_TABLE \ |
| 177 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 178 | |
| 179 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
| 180 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
| 181 | |
| 182 | /* Use the HUSH parser */ |
| 183 | #define CFG_HUSH_PARSER |
| 184 | #ifdef CFG_HUSH_PARSER |
| 185 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 186 | #endif |
| 187 | |
| 188 | /* I2C */ |
| 189 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
| 190 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 191 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 192 | #define CFG_I2C_SLAVE 0x7F |
| 193 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
| 194 | |
| 195 | /* |
| 196 | * EEPROM configuration |
| 197 | */ |
| 198 | #define CFG_I2C_EEPROM_ADDR 0x58 |
| 199 | #define CFG_I2C_EEPROM_ADDR_LEN 1 |
| 200 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 |
| 201 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 |
| 202 | |
| 203 | /* |
| 204 | * RTC configuration |
| 205 | */ |
| 206 | #define CONFIG_RTC_PCF8563 |
| 207 | #define CFG_I2C_RTC_ADDR 0x51 |
| 208 | |
| 209 | /* RapidIO MMU */ |
| 210 | #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ |
| 211 | #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE |
| 212 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ |
| 213 | |
| 214 | /* |
| 215 | * General PCI |
| 216 | * Addresses are mapped 1-1. |
| 217 | */ |
| 218 | #define CFG_PCI1_MEM_BASE 0x80000000 |
| 219 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
| 220 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
| 221 | #define CFG_PCI1_IO_BASE 0xe2000000 |
| 222 | #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE |
| 223 | #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ |
| 224 | |
| 225 | #if defined(CONFIG_PCI) |
| 226 | |
| 227 | #define CONFIG_NET_MULTI |
| 228 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 229 | |
| 230 | #undef CONFIG_EEPRO100 |
| 231 | #undef CONFIG_TULIP |
| 232 | |
| 233 | #if !defined(CONFIG_PCI_PNP) |
| 234 | #define PCI_ENET0_IOADDR 0xe0000000 |
| 235 | #define PCI_ENET0_MEMADDR 0xe0000000 |
| 236 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
| 237 | #endif |
| 238 | |
| 239 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 240 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
| 241 | |
| 242 | #endif /* CONFIG_PCI */ |
| 243 | |
| 244 | |
| 245 | #if defined(CONFIG_TSEC_ENET) |
| 246 | |
| 247 | #ifndef CONFIG_NET_MULTI |
| 248 | #define CONFIG_NET_MULTI 1 |
| 249 | #endif |
| 250 | |
| 251 | #define CONFIG_MII 1 /* MII PHY management */ |
| 252 | #define CONFIG_MPC85XX_TSEC1 1 |
| 253 | #define CONFIG_MPC85XX_TSEC2 1 |
| 254 | #define TSEC1_PHY_ADDR 2 |
| 255 | #define TSEC2_PHY_ADDR 3 |
| 256 | #define TSEC1_PHYIDX 0 |
| 257 | #define TSEC2_PHYIDX 0 |
| 258 | |
| 259 | #define CONFIG_MPC85XX_FEC 1 |
| 260 | #define FEC_PHY_ADDR 1 |
| 261 | #define FEC_PHYIDX 0 |
| 262 | |
| 263 | #define CONFIG_ETHPRIME "MOTO ENET0" |
| 264 | |
| 265 | #define CONFIG_HAS_ETH1 1 |
| 266 | #define CONFIG_HAS_ETH2 1 |
| 267 | |
| 268 | #endif /* CONFIG_TSEC_ENET */ |
| 269 | |
| 270 | |
| 271 | /* |
| 272 | * Environment |
| 273 | */ |
| 274 | #ifndef CFG_RAMBOOT |
| 275 | #define CFG_ENV_IS_IN_FLASH 1 |
| 276 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000) |
| 277 | #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
| 278 | #define CFG_ENV_SIZE 0x2000 |
| 279 | #else |
| 280 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ |
| 281 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
| 282 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
| 283 | #define CFG_ENV_SIZE 0x2000 |
| 284 | #endif |
| 285 | |
| 286 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 287 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 288 | |
| 289 | #if defined(CFG_RAMBOOT) |
| 290 | #if defined(CONFIG_PCI) |
| 291 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
| 292 | | CFG_CMD_PING \ |
| 293 | | CFG_CMD_PCI \ |
| 294 | | CFG_CMD_I2C) \ |
| 295 | & \ |
| 296 | ~(CFG_CMD_ENV \ |
| 297 | | CFG_CMD_LOADS)) |
| 298 | #else |
| 299 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
| 300 | | CFG_CMD_PING \ |
| 301 | | CFG_CMD_I2C) \ |
| 302 | & \ |
| 303 | ~(CFG_CMD_ENV \ |
| 304 | | CFG_CMD_LOADS)) |
| 305 | #endif |
| 306 | #else |
| 307 | #if defined(CONFIG_PCI) |
| 308 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
| 309 | | CFG_CMD_EEPROM \ |
| 310 | | CFG_CMD_DATE \ |
| 311 | | CFG_CMD_PCI \ |
| 312 | | CFG_CMD_PING \ |
| 313 | | CFG_CMD_I2C) |
| 314 | #else |
| 315 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
| 316 | | CFG_CMD_EEPROM \ |
| 317 | | CFG_CMD_DATE \ |
| 318 | | CFG_CMD_PING \ |
| 319 | | CFG_CMD_I2C) |
| 320 | #endif |
| 321 | #endif |
| 322 | |
| 323 | #include <cmd_confdefs.h> |
| 324 | |
| 325 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 326 | |
| 327 | /* |
| 328 | * Miscellaneous configurable options |
| 329 | */ |
| 330 | #define CFG_LONGHELP /* undef to save memory */ |
| 331 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
| 332 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 333 | |
| 334 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 335 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 336 | #else |
| 337 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 338 | #endif |
| 339 | |
| 340 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 341 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 342 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 343 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
| 344 | #define CONFIG_LOOPW |
| 345 | |
| 346 | /* |
| 347 | * For booting Linux, the board info and command line data |
| 348 | * have to be in the first 8 MB of memory, since this is |
| 349 | * the maximum mapped by the Linux kernel during initialization. |
| 350 | */ |
| 351 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| 352 | |
| 353 | /* Cache Configuration */ |
| 354 | #define CFG_DCACHE_SIZE 32768 |
| 355 | #define CFG_CACHELINE_SIZE 32 |
| 356 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 357 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
| 358 | #endif |
| 359 | |
| 360 | /* |
| 361 | * Internal Definitions |
| 362 | * |
| 363 | * Boot Flags |
| 364 | */ |
| 365 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 366 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 367 | |
| 368 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 369 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 370 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 371 | #endif |
| 372 | |
| 373 | |
| 374 | /* |
| 375 | * Environment Configuration |
| 376 | */ |
| 377 | |
| 378 | /* The mac addresses for all ethernet interface */ |
| 379 | #if defined(CONFIG_TSEC_ENET) |
| 380 | #define CONFIG_ETHADDR 00:40:42:01:00:00 |
| 381 | #define CONFIG_ETH1ADDR 00:40:42:01:00:01 |
| 382 | #define CONFIG_ETH2ADDR 00:40:42:01:00:02 |
| 383 | #endif |
| 384 | |
| 385 | #define CONFIG_IPADDR 192.168.0.103 |
| 386 | |
| 387 | #define CONFIG_HOSTNAME PM854 |
| 388 | #define CONFIG_ROOTPATH /opt/eldk30/ppc_82xx |
| 389 | #define CONFIG_BOOTFILE uImage |
| 390 | |
| 391 | #define CONFIG_SERVERIP 192.168.0.54 |
| 392 | #define CONFIG_GATEWAYIP 192.168.0.1 |
| 393 | #define CONFIG_NETMASK 255.255.255.0 |
| 394 | |
| 395 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
| 396 | |
| 397 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
| 398 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 399 | |
| 400 | #define CONFIG_BAUDRATE 9600 |
| 401 | |
| 402 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 403 | "netdev=eth0\0" \ |
| 404 | "consoledev=ttyS0\0" \ |
| 405 | "ramdiskaddr=400000\0" \ |
| 406 | "ramdiskfile=uRamdisk\0" |
| 407 | |
| 408 | #define CONFIG_NFSBOOTCOMMAND \ |
| 409 | "setenv bootargs root=/dev/nfs rw " \ |
| 410 | "nfsroot=$serverip:$rootpath " \ |
| 411 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 412 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 413 | "tftp $loadaddr $bootfile;" \ |
| 414 | "bootm $loadaddr" |
| 415 | |
| 416 | #define CONFIG_RAMBOOTCOMMAND \ |
| 417 | "setenv bootargs root=/dev/ram rw " \ |
| 418 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 419 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 420 | "tftp $loadaddr $bootfile;" \ |
| 421 | "bootm $loadaddr $ramdiskaddr" |
| 422 | |
| 423 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
| 424 | |
| 425 | #endif /* __CONFIG_H */ |