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wdenk75dc29e2002-08-19 15:30:13 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
39#define CONFIG_SM850 1 /*...on a MPC850 Service Module */
40
41#undef CONFIG_8xx_CONS_SMC1 /* SMC1 not usable because Ethernet on SCC3 */
42#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
43#undef CONFIG_8xx_CONS_NONE
44#define CONFIG_BAUDRATE 115200
45#if 0
46#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47#else
48#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49#endif
50
51#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
52
53#define CONFIG_BOARD_TYPES 1 /* support board types */
54
55#undef CONFIG_BOOTARGS
56#define CONFIG_BOOTCOMMAND \
57 "bootp; " \
58 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
59 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
60 "bootm"
61
62#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
63#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
64
65#undef CONFIG_WATCHDOG /* watchdog disabled */
66
67#undef CONFIG_STATUS_LED /* Status LED not enabled */
68
69#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
70
71#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
72
73#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
74
75#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
76 CFG_CMD_DHCP | \
77 CFG_CMD_DATE )
78
79/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
80#include <cmd_confdefs.h>
81
82/*
83 * Miscellaneous configurable options
84 */
85#define CFG_LONGHELP /* undef to save memory */
86#define CFG_PROMPT "=> " /* Monitor Command Prompt */
87#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && defined(KGDB_DEBUG)
88#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
89#else
90#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
91#endif
92#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
93#define CFG_MAXARGS 16 /* max number of command args */
94#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
95
96#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
97#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
98
99#define CFG_LOAD_ADDR 0x100000 /* default load address */
100
101#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
102
103#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
104
105/*
106 * Low Level Configuration Settings
107 * (address mappings, register initial values, etc.)
108 * You should know what you are doing if you make changes here.
109 */
110/*-----------------------------------------------------------------------
111 * Internal Memory Mapped Register
112 */
113#define CFG_IMMR 0xFFF00000
114
115/*-----------------------------------------------------------------------
116 * Definitions for initial stack pointer and data area (in DPRAM)
117 */
118#define CFG_INIT_RAM_ADDR CFG_IMMR
119#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
120#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
121#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
122#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
123
124/*-----------------------------------------------------------------------
125 * Start addresses for the final memory configuration
126 * (Set up by the startup code)
127 * Please note that CFG_SDRAM_BASE _must_ start at 0
128 */
129#define CFG_SDRAM_BASE 0x00000000
130#define CFG_FLASH_BASE 0x40000000
131#if defined(DEBUG)
132#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
133#else
134#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
135#endif
136#define CFG_MONITOR_BASE CFG_FLASH_BASE
137#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
138
139/*
140 * For booting Linux, the board info and command line data
141 * have to be in the first 8 MB of memory, since this is
142 * the maximum mapped by the Linux kernel during initialization.
143 */
144#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
145
146/*-----------------------------------------------------------------------
147 * FLASH organization
148 */
149#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
150#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
151
152#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
153#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
154
155#define CFG_ENV_IS_IN_FLASH 1
156#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
157#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
158
159/*-----------------------------------------------------------------------
160 * Hardware Information Block
161 */
162#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
163#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
164#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
165
166/*-----------------------------------------------------------------------
167 * Cache Configuration
168 */
169#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
170#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
171#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
172#endif
173
174/*-----------------------------------------------------------------------
175 * SYPCR - System Protection Control 11-9
176 * SYPCR can only be written once after reset!
177 *-----------------------------------------------------------------------
178 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
179 */
180#if defined(CONFIG_WATCHDOG)
181#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
182 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
183#else
184#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
185#endif
186
187/*-----------------------------------------------------------------------
188 * SIUMCR - SIU Module Configuration 11-6
189 *-----------------------------------------------------------------------
190 * PCMCIA config., multi-function pin tri-state
191 */
192#ifndef CONFIG_CAN_DRIVER
193#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
194#else /* we must activate GPL5 in the SIUMCR for CAN */
195#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
196#endif /* CONFIG_CAN_DRIVER */
197
198/*-----------------------------------------------------------------------
199 * TBSCR - Time Base Status and Control 11-26
200 *-----------------------------------------------------------------------
201 * Clear Reference Interrupt Status, Timebase freezing enabled
202 */
203#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
204
205/*-----------------------------------------------------------------------
206 * RTCSC - Real-Time Clock Status and Control Register 11-27
207 *-----------------------------------------------------------------------
208 */
209#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
210
211/*-----------------------------------------------------------------------
212 * PISCR - Periodic Interrupt Status and Control 11-31
213 *-----------------------------------------------------------------------
214 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
215 */
216#define CFG_PISCR (PISCR_PS | PISCR_PITF)
217
218/*-----------------------------------------------------------------------
219 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
220 *-----------------------------------------------------------------------
221 * Reset PLL lock status sticky bit, timer expired status bit and timer
222 * interrupt status bit
223 *
224 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
225 */
226#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
227#define CFG_PLPRCR \
228 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
229#else
230#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
231#endif /* TQM8xxL_80MHz */
232
233/*-----------------------------------------------------------------------
234 * SCCR - System Clock and reset Control Register 15-27
235 *-----------------------------------------------------------------------
236 * Set clock output, timebase and RTC source and divider,
237 * power management and some other internal clocks
238 */
239#define SCCR_MASK SCCR_EBDF11
240#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
241#define CFG_SCCR (/* SCCR_TBS | */ \
242 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
243 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
244 SCCR_DFALCD00)
245#else /* up to 50 MHz we use a 1:1 clock */
246#define CFG_SCCR (SCCR_TBS | \
247 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
248 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
249 SCCR_DFALCD00)
250#endif /* TQM8xxL_80MHz */
251
252/*-----------------------------------------------------------------------
253 * PCMCIA stuff
254 *-----------------------------------------------------------------------
255 *
256 */
257#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
258#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
259#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
260#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
261#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
262#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
263#define CFG_PCMCIA_IO_ADDR (0xEC000000)
264#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
265
266/*-----------------------------------------------------------------------
267 *
268 *-----------------------------------------------------------------------
269 *
270 */
wdenk75dc29e2002-08-19 15:30:13 +0000271#define CFG_DER 0
272
273/*
274 * Init Memory Controller:
275 *
276 * BR0/1 and OR0/1 (FLASH)
277 */
278
279#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
280#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
281
282/* used to re-map FLASH both when starting from SRAM or FLASH:
283 * restrict access enough to keep SRAM working (if any)
284 * but not too much to meddle with FLASH accesses
285 */
286#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
287#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
288
289/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
290#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
291 OR_SCY_5_CLK | OR_EHTR)
292
293#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
294#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
295#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
296
297#define CFG_OR1_REMAP CFG_OR0_REMAP
298#define CFG_OR1_PRELIM CFG_OR0_PRELIM
299#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
300
301/*
302 * BR2/3 and OR2/3 (SDRAM)
303 *
304 */
305#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
306#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
307#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
308
309/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
310#define CFG_OR_TIMING_SDRAM 0x00000A00
311
312#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
313#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
314
315#ifndef CONFIG_CAN_DRIVER
316#define CFG_OR3_PRELIM CFG_OR2_PRELIM
317#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
318#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
319#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
320#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
321#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
322#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
323 BR_PS_8 | BR_MS_UPMB | BR_V )
324#endif /* CONFIG_CAN_DRIVER */
325
326/*
327 * Memory Periodic Timer Prescaler
328 */
329
330/* periodic timer for refresh */
331#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
332
333/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
334#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
335#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
336
337/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
338#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
339#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
340
341/*
342 * MAMR settings for SDRAM
343 */
344
345/* 8 column SDRAM */
346#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
347 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
348 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
349/* 9 column SDRAM */
350#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
351 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
352 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
353
354
355/*
356 * Internal Definitions
357 *
358 * Boot Flags
359 */
360#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
361#define BOOTFLAG_WARM 0x02 /* Software reboot */
362
363#endif /* __CONFIG_H */