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wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2003
3 * Texas Instruments.
4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
6 *
7 * (C) Copyright 2004
8 * ARM Ltd.
9 * Philippe Robin, <philippe.robin@arm.com>
10 * Configuration for Compact Integrator board.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
wdenk5a95f6f2005-01-12 00:38:03 +000038#if 1
wdenk3d3befa2004-03-14 15:06:13 +000039#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
wdenk5a95f6f2005-01-12 00:38:03 +000040#else
41#define CONFIG_ARM946ES 1 /* This is an arm946es CPU core */
42#endif
wdenk3d3befa2004-03-14 15:06:13 +000043#define CONFIG_INTEGRATOR 1 /* in an Integrator board */
44#define CONFIG_ARCH_CINTEGRATOR 1 /* Specifically, a CP */
45
46
47#define CFG_MEMTEST_START 0x100000
48#define CFG_MEMTEST_END 0x10000000
49#define CFG_HZ (1000000 / 256) /* Timer 1 is clocked at 1Mhz, with 256 divider */
50#define CFG_TIMERBASE 0x13000100
51
52#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
53#define CONFIG_SETUP_MEMORY_TAGS 1
54#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
55/*
56 * Size of malloc() pool
57 */
wdenk5a95f6f2005-01-12 00:38:03 +000058#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenk42dfe7a2004-03-14 22:25:36 +000059#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk3d3befa2004-03-14 15:06:13 +000060
61/*
62 * Hardware drivers
63 */
64#define CONFIG_DRIVER_SMC91111
65#define CONFIG_SMC_USE_32_BIT
66#define CONFIG_SMC91111_BASE 0xC8000000
67#undef CONFIG_SMC91111_EXT_PHY
68
69/*
70 * NS16550 Configuration
71 */
72#define CFG_PL011_SERIAL
wdenk6705d812004-08-02 23:22:59 +000073#define CONFIG_PL011_CLOCK 14745600
74#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
wdenk3d3befa2004-03-14 15:06:13 +000075#define CONFIG_CONS_INDEX 0
wdenk5a95f6f2005-01-12 00:38:03 +000076#define CONFIG_BAUDRATE 38400
wdenk3d3befa2004-03-14 15:06:13 +000077#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
78#define CFG_SERIAL0 0x16000000
79#define CFG_SERIAL1 0x17000000
80
wdenk5a95f6f2005-01-12 00:38:03 +000081/*
82#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_PCI)
83*/
84#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | \
85 CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV \
86 )
87
88/* #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
wdenk3d3befa2004-03-14 15:06:13 +000089
90/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
91#include <cmd_confdefs.h>
92
wdenk5a95f6f2005-01-12 00:38:03 +000093#if 0
wdenk3d3befa2004-03-14 15:06:13 +000094#define CONFIG_BOOTDELAY 2
wdenk42dfe7a2004-03-14 22:25:36 +000095#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0"
wdenk3d3befa2004-03-14 15:06:13 +000096#define CONFIG_BOOTCOMMAND "bootp ; bootm"
wdenk5a95f6f2005-01-12 00:38:03 +000097#endif
wdenk3d3befa2004-03-14 15:06:13 +000098
99/*
100 * Miscellaneous configurable options
101 */
wdenk5a95f6f2005-01-12 00:38:03 +0000102#define CFG_LONGHELP /* undef to save memory */
wdenk3d3befa2004-03-14 15:06:13 +0000103#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
wdenk5a95f6f2005-01-12 00:38:03 +0000104#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk3d3befa2004-03-14 15:06:13 +0000105/* Print Buffer Size */
106#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
wdenk5a95f6f2005-01-12 00:38:03 +0000107#define CFG_MAXARGS 16 /* max number of command args */
108#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
wdenk3d3befa2004-03-14 15:06:13 +0000109
110#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
111#define CFG_LOAD_ADDR 0x7fc0 /* default load address */
112
113/*-----------------------------------------------------------------------
114 * Stack sizes
115 *
116 * The stack sizes are set up in start.S using the settings below
117 */
118#define CONFIG_STACKSIZE (128*1024) /* regular stack */
119#ifdef CONFIG_USE_IRQ
120#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
121#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
122#endif
123
124/*-----------------------------------------------------------------------
125 * Physical Memory Map
126 */
wdenk5a95f6f2005-01-12 00:38:03 +0000127#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
wdenk3d3befa2004-03-14 15:06:13 +0000128#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
wdenk5a95f6f2005-01-12 00:38:03 +0000129#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
wdenk3d3befa2004-03-14 15:06:13 +0000130
131/*-----------------------------------------------------------------------
132 * FLASH and environment organization
133 */
wdenk5a95f6f2005-01-12 00:38:03 +0000134#define CFG_FLASH_BASE 0x24000000
135#define CFG_MAX_FLASH_SECT 64
wdenk3d3befa2004-03-14 15:06:13 +0000136#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
137#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
wdenk3d3befa2004-03-14 15:06:13 +0000138#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
139#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
wdenk3d3befa2004-03-14 15:06:13 +0000140
wdenk5a95f6f2005-01-12 00:38:03 +0000141#define CFG_MONITOR_BASE 0x24F40000
142#define CFG_ENV_IS_IN_FLASH
143#define CFG_ENV_ADDR 0x24F00000
144#define CFG_ENV_SECT_SIZE 0x40000 /* 256KB */
145#define CFG_ENV_SIZE 8192 /* 8KB */
146
147#endif /* __CONFIG_H */