blob: 9ed38463cd81de4906bccefced46cd973f639f78 [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jmonkman@adventnetworks.com>
12 *
13 * (C) Copyright 2001
14 * Advent Networks, Inc. <http://www.adventnetworks.com>
15 * Oliver Brown <obrown@adventnetworks.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36/*********************************************************************/
37/* DESCRIPTION:
38 * This file contains the board configuartion for the GW8260 board.
39 *
40 * MODULE DEPENDENCY:
41 * None
42 *
43 * RESTRICTIONS/LIMITATIONS:
44 * None
45 *
46 * Copyright (c) 2001, Advent Networks, Inc.
47 */
48/*********************************************************************/
49
50#ifndef __CONFIG_H
51#define __CONFIG_H
52
53/* Enable debug prints */
wdenkfe8c2802002-11-03 00:38:21 +000054#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
55
56/* What is the oscillator's (UX2) frequency in Hz? */
57#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
58
59/*-----------------------------------------------------------------------
60 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
61 *-----------------------------------------------------------------------
62 * What should MODCK_H be? It is dependent on the oscillator
63 * frequency, MODCK[1-3], and desired CPM and core frequencies.
64 * Here are some example values (all frequencies are in MHz):
65 *
66 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
67 * ------- ---------- --- --- ---- ----- ----- -----
68 * 0x5 0x5 66 133 133 Open Close Open
69 * 0x5 0x6 66 133 166 Open Open Close
70 * 0x5 0x7 66 133 200 Open Open Open
71 * 0x6 0x0 66 133 233 Close Close Close
72 * 0x6 0x1 66 133 266 Close Close Open
73 * 0x6 0x2 66 133 300 Close Open Close
74 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_SBC_MODCK_H 0x05
wdenkfe8c2802002-11-03 00:38:21 +000076
77/* Define this if you want to boot from 0x00000100. If you don't define
78 * this, you will need to program the bootloader to 0xfff00000, and
79 * get the hardware reset config words at 0xfe000000. The simplest
80 * way to do that is to program the bootloader at both addresses.
81 * It is suggested that you just let U-Boot live at 0x00000000.
82 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_SBC_BOOT_LOW 1
wdenkfe8c2802002-11-03 00:38:21 +000084
85/* What should the base address of the main FLASH be and how big is
86 * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
87 * The main FLASH is whichever is connected to *CS0. U-Boot expects
88 * this to be the SIMM.
89 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_FLASH0_BASE 0x40000000
91#define CONFIG_SYS_FLASH0_SIZE 8
wdenkfe8c2802002-11-03 00:38:21 +000092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093/* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot.
wdenkfe8c2802002-11-03 00:38:21 +000094 * Note: the 'flashchecksum' environment variable must also be set to 'y'.
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_FLASH_CHECKSUM
wdenkfe8c2802002-11-03 00:38:21 +000097
98/* What should be the base address of SDRAM DIMM and how big is
99 * it (in Mbytes)?
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_SDRAM0_BASE 0x00000000
102#define CONFIG_SYS_SDRAM0_SIZE 64
wdenkfe8c2802002-11-03 00:38:21 +0000103
104/*
105 * DRAM tests
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106 * CONFIG_SYS_DRAM_TEST - enables the following tests.
wdenkfe8c2802002-11-03 00:38:21 +0000107 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108 * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
wdenkfe8c2802002-11-03 00:38:21 +0000109 * Environment variable 'test_dram_data' must be
110 * set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
wdenkfe8c2802002-11-03 00:38:21 +0000112 * addressable. Environment variable
113 * 'test_dram_address' must be set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114 * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
wdenkfe8c2802002-11-03 00:38:21 +0000115 * This test takes about 6 minutes to test 64 MB.
116 * Environment variable 'test_dram_walk' must be
117 * set to 'y'.
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DRAM_TEST
120#if defined(CONFIG_SYS_DRAM_TEST)
121#define CONFIG_SYS_DRAM_TEST_DATA
122#define CONFIG_SYS_DRAM_TEST_ADDRESS
123#define CONFIG_SYS_DRAM_TEST_WALK
124#endif /* CONFIG_SYS_DRAM_TEST */
wdenkfe8c2802002-11-03 00:38:21 +0000125
126/*
127 * GW8260 with 16 MB DIMM:
128 *
129 * 0x0000 0000 Exception Vector code, 8k
130 * :
131 * 0x0000 1FFF
132 * 0x0000 2000 Free for Application Use
133 * :
134 * :
135 *
136 * :
137 * :
138 * 0x00F5 FF30 Monitor Stack (Growing downward)
139 * Monitor Stack Buffer (0x80)
140 * 0x00F5 FFB0 Board Info Data
141 * 0x00F6 0000 Malloc Arena
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200142 * : CONFIG_ENV_SECT_SIZE, 256k
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 * : CONFIG_SYS_MALLOC_LEN, 128k
wdenkfe8c2802002-11-03 00:38:21 +0000144 * 0x00FC 0000 RAM Copy of Monitor Code
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 * : CONFIG_SYS_MONITOR_LEN, 256k
146 * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
wdenkfe8c2802002-11-03 00:38:21 +0000147 */
148
149/*
150 * GW8260 with 64 MB DIMM:
151 *
152 * 0x0000 0000 Exception Vector code, 8k
153 * :
154 * 0x0000 1FFF
155 * 0x0000 2000 Free for Application Use
156 * :
157 * :
158 *
159 * :
160 * :
161 * 0x03F5 FF30 Monitor Stack (Growing downward)
162 * Monitor Stack Buffer (0x80)
163 * 0x03F5 FFB0 Board Info Data
164 * 0x03F6 0000 Malloc Arena
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200165 * : CONFIG_ENV_SECT_SIZE, 256k
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166 * : CONFIG_SYS_MALLOC_LEN, 128k
wdenkfe8c2802002-11-03 00:38:21 +0000167 * 0x03FC 0000 RAM Copy of Monitor Code
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 * : CONFIG_SYS_MONITOR_LEN, 256k
169 * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
wdenkfe8c2802002-11-03 00:38:21 +0000170 */
171
172
173/*
174 * select serial console configuration
175 *
176 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
177 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
178 * for SCC).
179 *
180 * if CONFIG_CONS_NONE is defined, then the serial console routines must
181 * defined elsewhere.
182 */
183#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
184#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
185#undef CONFIG_CONS_NONE /* define if console on neither */
186#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
187
188/*
189 * select ethernet configuration
190 *
191 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
192 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
193 * for FCC)
194 *
195 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500196 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkfe8c2802002-11-03 00:38:21 +0000197 */
198
199#undef CONFIG_ETHER_ON_SCC
200#define CONFIG_ETHER_ON_FCC
201#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
202
203#ifdef CONFIG_ETHER_ON_SCC
204#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
205#endif /* CONFIG_ETHER_ON_SCC */
206
207#ifdef CONFIG_ETHER_ON_FCC
208#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
209#define CONFIG_MII /* MII PHY management */
210#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
211/*
212 * Port pins used for bit-banged MII communictions (if applicable).
213 */
214#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200215
216#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
217 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
218#define MDC_DECLARE MDIO_DECLARE
219
wdenkfe8c2802002-11-03 00:38:21 +0000220#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
221#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
222#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
223
224#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
wdenk8bde7f72003-06-27 21:31:46 +0000225 else iop->pdat &= ~0x00400000
wdenkfe8c2802002-11-03 00:38:21 +0000226
227#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
wdenk8bde7f72003-06-27 21:31:46 +0000228 else iop->pdat &= ~0x00200000
wdenkfe8c2802002-11-03 00:38:21 +0000229
230#define MIIDELAY udelay(1)
231#endif /* CONFIG_ETHER_ON_FCC */
232
233#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
234
235/*
236 * - Rx-CLK is CLK13
237 * - Tx-CLK is CLK14
238 * - Select bus for bd/buffers (see 28-13)
239 * - Enable Full Duplex in FSMR
240 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
242# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
243# define CONFIG_SYS_CPMFCR_RAMTYPE 0
244# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkfe8c2802002-11-03 00:38:21 +0000245
246#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
247
248/*
249 * - Rx-CLK is CLK15
250 * - Tx-CLK is CLK16
251 * - Select bus for bd/buffers (see 28-13)
252 * - Enable Full Duplex in FSMR
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
255# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
256# define CONFIG_SYS_CPMFCR_RAMTYPE 0
257# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkfe8c2802002-11-03 00:38:21 +0000258
259#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
260
261/* Define this to reserve an entire FLASH sector (256 KB) for
262 * environment variables. Otherwise, the environment will be
263 * put in the same sector as U-Boot, and changing variables
264 * will erase U-Boot temporarily
265 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200266#define CONFIG_ENV_IN_OWN_SECT
wdenkfe8c2802002-11-03 00:38:21 +0000267
268/* Define to allow the user to overwrite serial and ethaddr */
269#define CONFIG_ENV_OVERWRITE
270
271/* What should the console's baud rate be? */
272#define CONFIG_BAUDRATE 115200
273
274/* Ethernet MAC address - This is set to all zeros to force an
275 * an error if we use BOOTP without setting
276 * the MAC address
277 */
278#define CONFIG_ETHADDR 00:00:00:00:00:00
279
280/* Set to a positive value to delay for running BOOTCOMMAND */
281#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
282
283/* Be selective on what keys can delay or stop the autoboot process
284 * To stop use: " "
285 */
286#define CONFIG_AUTOBOOT_KEYED
Stefan Roesef2302d42008-08-06 14:05:38 +0200287#define CONFIG_AUTOBOOT_PROMPT \
288 "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
wdenkfe8c2802002-11-03 00:38:21 +0000289#define CONFIG_AUTOBOOT_STOP_STR " "
290#undef CONFIG_AUTOBOOT_DELAY_STR
291#define DEBUG_BOOTKEYS 0
292
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500293/*
294 * BOOTP options
wdenkfe8c2802002-11-03 00:38:21 +0000295 */
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500296#define CONFIG_BOOTP_SUBNETMASK
297#define CONFIG_BOOTP_GATEWAY
298#define CONFIG_BOOTP_HOSTNAME
299#define CONFIG_BOOTP_BOOTPATH
300
301#define CONFIG_BOOTP_BOOTFILESIZE
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200302#define CONFIG_BOOTP_DNS
wdenkfe8c2802002-11-03 00:38:21 +0000303
304/* undef this to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_LONGHELP
wdenkfe8c2802002-11-03 00:38:21 +0000306
307/* Monitor Command Prompt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_PROMPT "=> "
wdenkfe8c2802002-11-03 00:38:21 +0000309
Jon Loeliger72eb0ef2007-07-04 22:32:19 -0500310
311/*
312 * Command line configuration.
313 */
314#include <config_cmd_default.h>
315
316#define CONFIG_CMD_BEDBUG
317#define CONFIG_CMD_ELF
318#define CONFIG_CMD_ASKENV
319#define CONFIG_CMD_REGINFO
320#define CONFIG_CMD_IMMAP
321#define CONFIG_CMD_MII
322
323#undef CONFIG_CMD_KGDB
324
wdenkfe8c2802002-11-03 00:38:21 +0000325
326/* Where do the internal registers live? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_IMMR 0xf0000000
wdenkfe8c2802002-11-03 00:38:21 +0000328
329/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_HUSH_PARSER
331#ifdef CONFIG_SYS_HUSH_PARSER
332#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkfe8c2802002-11-03 00:38:21 +0000333#endif
334
335/* What is the address of IO controller */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_IO_BASE 0xe0000000
wdenkfe8c2802002-11-03 00:38:21 +0000337
338/*****************************************************************************
339 *
340 * You should not have to modify any of the following settings
341 *
342 *****************************************************************************/
343
344#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
345#define CONFIG_GW8260 1 /* on an GW8260 Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500346#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkfe8c2802002-11-03 00:38:21 +0000347
wdenkfe8c2802002-11-03 00:38:21 +0000348/*
349 * Miscellaneous configurable options
350 */
Jon Loeliger72eb0ef2007-07-04 22:32:19 -0500351#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000353#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000355#endif
356
357/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
wdenkfe8c2802002-11-03 00:38:21 +0000359
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
wdenkfe8c2802002-11-03 00:38:21 +0000361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000363
364/* Convert clocks to MHZ when passing board info to kernel.
365 * This must be defined for eariler 2.4 kernels (~2.4.4).
366 */
367#define CONFIG_CLOCKS_IN_MHZ
368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
370#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkfe8c2802002-11-03 00:38:21 +0000371
372
373/* memtest works from the end of the exception vector table
374 * to the end of the DRAM less monitor and malloc area
375 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_MEMTEST_START 0x2000
wdenkfe8c2802002-11-03 00:38:21 +0000377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
wdenkfe8c2802002-11-03 00:38:21 +0000379
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
381 + CONFIG_SYS_MALLOC_LEN \
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200382 + CONFIG_ENV_SECT_SIZE \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383 + CONFIG_SYS_STACK_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000384
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
386 - CONFIG_SYS_MEM_END_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000387
388/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkfe8c2802002-11-03 00:38:21 +0000390
391/*
392 * Low Level Configuration Settings
393 * (address mappings, register initial values, etc.)
394 * You should know what you are doing if you make changes here.
395 */
396
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
398#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
399#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
400#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
wdenkfe8c2802002-11-03 00:38:21 +0000401
402/*-----------------------------------------------------------------------
403 * Hard Reset Configuration Words
404 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#if defined(CONFIG_SYS_SBC_BOOT_LOW)
406# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenkfe8c2802002-11-03 00:38:21 +0000407#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
409#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
wdenkfe8c2802002-11-03 00:38:21 +0000410
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411/* get the HRCW ISB field from CONFIG_SYS_IMMR */
412#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
413 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
414 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenkfe8c2802002-11-03 00:38:21 +0000415
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \
wdenk8bde7f72003-06-27 21:31:46 +0000417 HRCW_DPPC11 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418 CONFIG_SYS_SBC_HRCW_IMMR | \
wdenk8bde7f72003-06-27 21:31:46 +0000419 HRCW_MMR00 | \
420 HRCW_LBPC11 | \
421 HRCW_APPC10 | \
422 HRCW_CS10PC00 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
424 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
wdenkfe8c2802002-11-03 00:38:21 +0000425
426/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_HRCW_SLAVE1 0
428#define CONFIG_SYS_HRCW_SLAVE2 0
429#define CONFIG_SYS_HRCW_SLAVE3 0
430#define CONFIG_SYS_HRCW_SLAVE4 0
431#define CONFIG_SYS_HRCW_SLAVE5 0
432#define CONFIG_SYS_HRCW_SLAVE6 0
433#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkfe8c2802002-11-03 00:38:21 +0000434
435/*-----------------------------------------------------------------------
436 * Definitions for initial stack pointer and data area (in DPRAM)
437 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
439#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
440#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
441#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
442#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkfe8c2802002-11-03 00:38:21 +0000443
444/*-----------------------------------------------------------------------
445 * Start addresses for the final memory configuration
446 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
448 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
wdenkfe8c2802002-11-03 00:38:21 +0000449 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000451
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
453#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000454
455/*
456 * For booting Linux, the board info and command line data
457 * have to be in the first 8 MB of memory, since this is
458 * the maximum mapped by the Linux kernel during initialization.
459 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000461
462/*-----------------------------------------------------------------------
463 * FLASH and environment organization
464 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
466#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
wdenkfe8c2802002-11-03 00:38:21 +0000467
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
469#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
wdenkfe8c2802002-11-03 00:38:21 +0000470
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200471#define CONFIG_ENV_IS_IN_FLASH 1
wdenkfe8c2802002-11-03 00:38:21 +0000472
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200473#ifdef CONFIG_ENV_IN_OWN_SECT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + (256 * 1024))
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200475# define CONFIG_ENV_SECT_SIZE (256 * 1024)
wdenkfe8c2802002-11-03 00:38:21 +0000476#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200477# define CONFIG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478# define CONFIG_ENV_ADD ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200479# define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */
480#endif /* CONFIG_ENV_IN_OWN_SECT */
wdenkfe8c2802002-11-03 00:38:21 +0000481
482/*-----------------------------------------------------------------------
483 * Cache Configuration
484 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
wdenkfe8c2802002-11-03 00:38:21 +0000486
Jon Loeliger72eb0ef2007-07-04 22:32:19 -0500487#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkfe8c2802002-11-03 00:38:21 +0000489#endif
490
491/*-----------------------------------------------------------------------
492 * HIDx - Hardware Implementation-dependent Registers 2-11
493 *-----------------------------------------------------------------------
494 * HID0 also contains cache control - initially enable both caches and
495 * invalidate contents, then the final state leaves only the instruction
496 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
497 * but Soft reset does not.
498 *
499 * HID1 has only read-only information - nothing to set.
500 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
wdenk8bde7f72003-06-27 21:31:46 +0000502 HID0_DCE |\
503 HID0_ICFI |\
504 HID0_DCI |\
505 HID0_IFEM |\
506 HID0_ABE)
wdenkfe8c2802002-11-03 00:38:21 +0000507
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
wdenk8bde7f72003-06-27 21:31:46 +0000509 HID0_IFEM |\
510 HID0_ABE |\
511 HID0_EMCP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512#define CONFIG_SYS_HID2 0
wdenkfe8c2802002-11-03 00:38:21 +0000513
514/*-----------------------------------------------------------------------
515 * RMR - Reset Mode Register
516 *-----------------------------------------------------------------------
517 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518#define CONFIG_SYS_RMR 0
wdenkfe8c2802002-11-03 00:38:21 +0000519
520/*-----------------------------------------------------------------------
521 * BCR - Bus Configuration 4-25
522 *-----------------------------------------------------------------------
523 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524#define CONFIG_SYS_BCR (BCR_ETM)
wdenkfe8c2802002-11-03 00:38:21 +0000525
526/*-----------------------------------------------------------------------
527 * SIUMCR - SIU Module Configuration 4-31
528 *-----------------------------------------------------------------------
529 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200530#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
wdenk8bde7f72003-06-27 21:31:46 +0000531 SIUMCR_L2CPC00 |\
532 SIUMCR_APPC10 |\
533 SIUMCR_MMR00)
wdenkfe8c2802002-11-03 00:38:21 +0000534
535
536/*-----------------------------------------------------------------------
537 * SYPCR - System Protection Control 11-9
538 * SYPCR can only be written once after reset!
539 *-----------------------------------------------------------------------
540 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
541 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200542#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
wdenk8bde7f72003-06-27 21:31:46 +0000543 SYPCR_BMT |\
544 SYPCR_PBME |\
545 SYPCR_LBME |\
546 SYPCR_SWRI |\
547 SYPCR_SWP)
wdenkfe8c2802002-11-03 00:38:21 +0000548
549/*-----------------------------------------------------------------------
550 * TMCNTSC - Time Counter Status and Control 4-40
551 *-----------------------------------------------------------------------
552 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
553 * and enable Time Counter
554 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200555#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
wdenk8bde7f72003-06-27 21:31:46 +0000556 TMCNTSC_ALR |\
557 TMCNTSC_TCF |\
558 TMCNTSC_TCE)
wdenkfe8c2802002-11-03 00:38:21 +0000559
560/*-----------------------------------------------------------------------
561 * PISCR - Periodic Interrupt Status and Control 4-42
562 *-----------------------------------------------------------------------
563 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
564 * Periodic timer
565 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200566#define CONFIG_SYS_PISCR (PISCR_PS |\
wdenk8bde7f72003-06-27 21:31:46 +0000567 PISCR_PTF |\
568 PISCR_PTE)
wdenkfe8c2802002-11-03 00:38:21 +0000569
570/*-----------------------------------------------------------------------
571 * SCCR - System Clock Control 9-8
572 *-----------------------------------------------------------------------
573 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200574#define CONFIG_SYS_SCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000575
576/*-----------------------------------------------------------------------
577 * RCCR - RISC Controller Configuration 13-7
578 *-----------------------------------------------------------------------
579 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_RCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000581
582/*
583 * Initialize Memory Controller:
584 *
585 * Bank Bus Machine PortSz Device
586 * ---- --- ------- ------ ------
587 * 0 60x GPCM 32 bit FLASH (SIMM - 4MB)
588 * 1 60x GPCM 32 bit unused
589 * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
590 * 3 60x SDRAM 64 bit unused
591 * 4 Local GPCM 8 bit IO (on board - 64k)
592 * 5 60x GPCM 8 bit unused
593 * 6 60x GPCM 8 bit unused
594 * 7 60x GPCM 8 bit unused
595 *
596 */
597
598/*-----------------------------------------------------------------------
599 * BR0 - Base Register
600 * Ref: Section 10.3.1 on page 10-14
601 * OR0 - Option Register
602 * Ref: Section 10.3.2 on page 10-18
603 *-----------------------------------------------------------------------
604 */
605
606/* Bank 0,1 - FLASH SIMM
607 *
608 * This expects the FLASH SIMM to be connected to *CS0
609 * It consists of 4 AM29F016D parts.
610 *
611 * Note: For the 8 MB SIMM, *CS1 is unused.
612 */
613
614/* BR0 is configured as follows:
615 *
616 * - Base address of 0x40000000
617 * - 32 bit port size
618 * - Data errors checking is disabled
619 * - Read and write access
620 * - GPCM 60x bus
621 * - Access are handled by the memory controller according to MSEL
622 * - Not used for atomic operations
623 * - No data pipelining is done
624 * - Valid
625 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200626#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000627 BRx_PS_32 |\
628 BRx_MS_GPCM_P |\
629 BRx_V)
wdenkfe8c2802002-11-03 00:38:21 +0000630
631/* OR0 is configured as follows:
632 *
633 * - 8 MB
634 * - *BCTL0 is asserted upon access to the current memory bank
635 * - *CW / *WE are negated a quarter of a clock earlier
636 * - *CS is output at the same time as the address lines
637 * - Uses a clock cycle length of 5
638 * - *PSDVAL is generated internally by the memory controller
639 * unless *GTA is asserted earlier externally.
640 * - Relaxed timing is generated by the GPCM for accesses
641 * initiated to this memory region.
642 * - One idle clock is inserted between a read access from the
643 * current bank and the next access.
644 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200645#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000646 ORxG_CSNT |\
647 ORxG_ACS_DIV1 |\
648 ORxG_SCY_5_CLK |\
649 ORxG_TRLX |\
650 ORxG_EHTR)
wdenkfe8c2802002-11-03 00:38:21 +0000651
652/*-----------------------------------------------------------------------
653 * BR2 - Base Register
654 * Ref: Section 10.3.1 on page 10-14
655 * OR2 - Option Register
656 * Ref: Section 10.3.2 on page 10-16
657 *-----------------------------------------------------------------------
658 */
659
660/* Bank 2 - SDRAM DIMM
661 *
662 * 16MB DIMM: P/N
663 * 64MB DIMM: P/N 1W-8864X8-4-P1-EST or
664 * MT4LSDT864AG-10EB1 (Micron)
665 *
666 * Note: *CS3 is unused for this DIMM
667 */
668
669/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
670 *
671 * - Base address of 0x00000000
672 * - 64 bit port size (60x bus only)
673 * - Data errors checking is disabled
674 * - Read and write access
675 * - SDRAM 60x bus
676 * - Access are handled by the memory controller according to MSEL
677 * - Not used for atomic operations
678 * - No data pipelining is done
679 * - Valid
680 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200681#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000682 BRx_PS_64 |\
683 BRx_MS_SDRAM_P |\
684 BRx_V)
wdenkfe8c2802002-11-03 00:38:21 +0000685
686/* With a 16 MB DIMM, the OR2 is configured as follows:
687 *
688 * - 16 MB
689 * - 2 internal banks per device
690 * - Row start address bit is A9 with PSDMR[PBI] = 0
691 * - 11 row address lines
692 * - Back-to-back page mode
693 * - Internal bank interleaving within save device enabled
694 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200695#if (CONFIG_SYS_SDRAM0_SIZE == 16)
696#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000697 ORxS_BPD_2 |\
698 ORxS_ROWST_PBI0_A9 |\
699 ORxS_NUMR_11)
wdenkfe8c2802002-11-03 00:38:21 +0000700
701/* With a 16 MB DIMM, the PSDMR is configured as follows:
702 *
703 * - Page Based Interleaving,
704 * - Refresh Enable,
705 * - Address Multiplexing where A5 is output on A14 pin
706 * (A6 on A15, and so on),
707 * - use address pins A16-A18 as bank select,
708 * - A9 is output on SDA10 during an ACTIVATE command,
709 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
710 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
711 * is 3 clocks,
712 * - earliest timing for READ/WRITE command after ACTIVATE command is
713 * 2 clocks,
714 * - earliest timing for PRECHARGE after last data was read is 1 clock,
715 * - earliest timing for PRECHARGE after last data was written is 1 clock,
716 * - CAS Latency is 2.
717 */
718
719/*-----------------------------------------------------------------------
720 * PSDMR - 60x Bus SDRAM Mode Register
721 * Ref: Section 10.3.3 on page 10-21
722 *-----------------------------------------------------------------------
723 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200724#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenk8bde7f72003-06-27 21:31:46 +0000725 PSDMR_SDAM_A14_IS_A5 |\
726 PSDMR_BSMA_A16_A18 |\
727 PSDMR_SDA10_PBI0_A9 |\
728 PSDMR_RFRC_7_CLK |\
729 PSDMR_PRETOACT_3W |\
730 PSDMR_ACTTORW_2W |\
731 PSDMR_LDOTOPRE_1C |\
732 PSDMR_WRC_1C |\
733 PSDMR_CL_2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200734#endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */
wdenkfe8c2802002-11-03 00:38:21 +0000735
736/* With a 64 MB DIMM, the OR2 is configured as follows:
737 *
738 * - 64 MB
739 * - 4 internal banks per device
740 * - Row start address bit is A8 with PSDMR[PBI] = 0
741 * - 12 row address lines
742 * - Back-to-back page mode
743 * - Internal bank interleaving within save device enabled
744 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200745#if (CONFIG_SYS_SDRAM0_SIZE == 64)
746#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000747 ORxS_BPD_4 |\
748 ORxS_ROWST_PBI0_A8 |\
749 ORxS_NUMR_12)
wdenkfe8c2802002-11-03 00:38:21 +0000750
751/* With a 64 MB DIMM, the PSDMR is configured as follows:
752 *
753 * - Page Based Interleaving,
754 * - Refresh Enable,
755 * - Address Multiplexing where A5 is output on A14 pin
756 * (A6 on A15, and so on),
757 * - use address pins A14-A16 as bank select,
758 * - A9 is output on SDA10 during an ACTIVATE command,
759 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
760 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
761 * is 3 clocks,
762 * - earliest timing for READ/WRITE command after ACTIVATE command is
763 * 2 clocks,
764 * - earliest timing for PRECHARGE after last data was read is 1 clock,
765 * - earliest timing for PRECHARGE after last data was written is 1 clock,
766 * - CAS Latency is 2.
767 */
768
769/*-----------------------------------------------------------------------
770 * PSDMR - 60x Bus SDRAM Mode Register
771 * Ref: Section 10.3.3 on page 10-21
772 *-----------------------------------------------------------------------
773 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200774#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenk8bde7f72003-06-27 21:31:46 +0000775 PSDMR_SDAM_A14_IS_A5 |\
776 PSDMR_BSMA_A14_A16 |\
777 PSDMR_SDA10_PBI0_A9 |\
778 PSDMR_RFRC_7_CLK |\
779 PSDMR_PRETOACT_3W |\
780 PSDMR_ACTTORW_2W |\
781 PSDMR_LDOTOPRE_1C |\
782 PSDMR_WRC_1C |\
783 PSDMR_CL_2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200784#endif /* (CONFIG_SYS_SDRAM0_SIZE == 64) */
wdenkfe8c2802002-11-03 00:38:21 +0000785
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200786#define CONFIG_SYS_PSRT 0x0e
787#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
wdenkfe8c2802002-11-03 00:38:21 +0000788
789
790/*-----------------------------------------------------------------------
791 * BR4 - Base Register
792 * Ref: Section 10.3.1 on page 10-14
793 * OR4 - Option Register
794 * Ref: Section 10.3.2 on page 10-18
795 *-----------------------------------------------------------------------
796 */
797/* Bank 4 - Onboard Memory Mapped IO controller
798 *
799 * This expects the onboard IO controller to connected to *CS4 and
800 * the local bus.
801 * - Base address of 0xe0000000
802 * - 8 bit port size (local bus only)
803 * - Read and write access
804 * - GPCM local bus
805 * - Not used for atomic operations
806 * - No data pipelining is done
807 * - Valid
808 * - extended hold time
809 * - 11 wait states
810 */
811
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200812#ifdef CONFIG_SYS_IO_BASE
813# define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000814 BRx_PS_8 |\
815 BRx_MS_GPCM_L |\
816 BRx_V)
wdenkfe8c2802002-11-03 00:38:21 +0000817
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200818# define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
wdenk8bde7f72003-06-27 21:31:46 +0000819 ORxG_SCY_11_CLK |\
820 ORxG_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200821#endif /* CONFIG_SYS_IO_BASE */
wdenkfe8c2802002-11-03 00:38:21 +0000822
823/*
824 * Internal Definitions
825 *
826 * Boot Flags
827 */
828#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
829#define BOOTFLAG_WARM 0x02 /* Software reboot */
830
831#endif /* __CONFIG_H */