Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2015 - 2019 MediaTek Inc. |
| 4 | * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> |
| 5 | * Ryder Lee <ryder.lee@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <clk.h> |
| 10 | #include <dm.h> |
| 11 | #include <generic-phy.h> |
Simon Glass | 336d461 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 12 | #include <malloc.h> |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 13 | #include <mapmem.h> |
| 14 | #include <asm/io.h> |
Simon Glass | 336d461 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 15 | #include <dm/device_compat.h> |
Simon Glass | 61b29b8 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 16 | #include <dm/devres.h> |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 17 | |
| 18 | #include <dt-bindings/phy/phy.h> |
| 19 | |
| 20 | /* version V1 sub-banks offset base address */ |
| 21 | /* banks shared by multiple phys */ |
| 22 | #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 23 | #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 24 | #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 25 | /* u2 phy bank */ |
| 26 | #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 27 | /* u3/pcie/sata phy banks */ |
| 28 | #define SSUSB_SIFSLV_V1_U3PHYD 0x000 |
| 29 | #define SSUSB_SIFSLV_V1_U3PHYA 0x200 |
| 30 | |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 31 | #define U3P_USBPHYACR0 0x000 |
| 32 | #define PA0_RG_U2PLL_FORCE_ON BIT(15) |
| 33 | #define PA0_RG_USB20_INTR_EN BIT(5) |
| 34 | |
| 35 | #define U3P_USBPHYACR5 0x014 |
| 36 | #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) |
| 37 | #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) |
| 38 | #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) |
| 39 | #define PA5_RG_U2_HS_100U_U3_EN BIT(11) |
| 40 | |
| 41 | #define U3P_USBPHYACR6 0x018 |
| 42 | #define PA6_RG_U2_BC11_SW_EN BIT(23) |
| 43 | #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) |
| 44 | #define PA6_RG_U2_SQTH GENMASK(3, 0) |
| 45 | #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) |
| 46 | |
| 47 | #define U3P_U2PHYACR4 0x020 |
| 48 | #define P2C_RG_USB20_GPIO_CTL BIT(9) |
| 49 | #define P2C_USB20_GPIO_MODE BIT(8) |
| 50 | #define P2C_U2_GPIO_CTR_MSK \ |
| 51 | (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) |
| 52 | |
| 53 | #define U3P_U2PHYDTM0 0x068 |
| 54 | #define P2C_FORCE_UART_EN BIT(26) |
| 55 | #define P2C_FORCE_DATAIN BIT(23) |
| 56 | #define P2C_FORCE_DM_PULLDOWN BIT(21) |
| 57 | #define P2C_FORCE_DP_PULLDOWN BIT(20) |
| 58 | #define P2C_FORCE_XCVRSEL BIT(19) |
| 59 | #define P2C_FORCE_SUSPENDM BIT(18) |
| 60 | #define P2C_FORCE_TERMSEL BIT(17) |
| 61 | #define P2C_RG_DATAIN GENMASK(13, 10) |
| 62 | #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) |
| 63 | #define P2C_RG_DMPULLDOWN BIT(7) |
| 64 | #define P2C_RG_DPPULLDOWN BIT(6) |
| 65 | #define P2C_RG_XCVRSEL GENMASK(5, 4) |
| 66 | #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) |
| 67 | #define P2C_RG_SUSPENDM BIT(3) |
| 68 | #define P2C_RG_TERMSEL BIT(2) |
| 69 | #define P2C_DTM0_PART_MASK \ |
| 70 | (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ |
| 71 | P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ |
| 72 | P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ |
| 73 | P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL) |
| 74 | |
| 75 | #define U3P_U2PHYDTM1 0x06C |
| 76 | #define P2C_RG_UART_EN BIT(16) |
| 77 | #define P2C_FORCE_IDDIG BIT(9) |
| 78 | #define P2C_RG_VBUSVALID BIT(5) |
| 79 | #define P2C_RG_SESSEND BIT(4) |
| 80 | #define P2C_RG_AVALID BIT(2) |
| 81 | #define P2C_RG_IDDIG BIT(1) |
| 82 | |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 83 | #define U3P_U3_CHIP_GPIO_CTLD 0x0c |
| 84 | #define P3C_REG_IP_SW_RST BIT(31) |
| 85 | #define P3C_MCU_BUS_CK_GATE_EN BIT(30) |
| 86 | #define P3C_FORCE_IP_SW_RST BIT(29) |
| 87 | |
| 88 | #define U3P_U3_CHIP_GPIO_CTLE 0x10 |
| 89 | #define P3C_RG_SWRST_U3_PHYD BIT(25) |
| 90 | #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) |
| 91 | |
| 92 | #define U3P_U3_PHYA_REG0 0x000 |
| 93 | #define P3A_RG_CLKDRV_OFF GENMASK(3, 2) |
| 94 | #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) |
| 95 | |
| 96 | #define U3P_U3_PHYA_REG1 0x004 |
| 97 | #define P3A_RG_CLKDRV_AMP GENMASK(31, 29) |
| 98 | #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) |
| 99 | |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 100 | #define U3P_U3_PHYA_REG6 0x018 |
| 101 | #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) |
| 102 | #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) |
| 103 | |
| 104 | #define U3P_U3_PHYA_REG9 0x024 |
| 105 | #define P3A_RG_RX_DAC_MUX GENMASK(5, 1) |
| 106 | #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) |
| 107 | |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 108 | #define U3P_U3_PHYA_DA_REG0 0x100 |
| 109 | #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) |
| 110 | #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) |
| 111 | #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) |
| 112 | #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) |
| 113 | #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) |
| 114 | #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) |
| 115 | |
| 116 | #define U3P_U3_PHYA_DA_REG4 0x108 |
| 117 | #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) |
| 118 | #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) |
| 119 | #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) |
| 120 | |
| 121 | #define U3P_U3_PHYA_DA_REG5 0x10c |
| 122 | #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) |
| 123 | #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) |
| 124 | #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) |
| 125 | #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) |
| 126 | |
| 127 | #define U3P_U3_PHYA_DA_REG6 0x110 |
| 128 | #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) |
| 129 | #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) |
| 130 | |
| 131 | #define U3P_U3_PHYA_DA_REG7 0x114 |
| 132 | #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) |
| 133 | #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) |
| 134 | |
| 135 | #define U3P_U3_PHYA_DA_REG20 0x13c |
| 136 | #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) |
| 137 | #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) |
| 138 | |
| 139 | #define U3P_U3_PHYA_DA_REG25 0x148 |
| 140 | #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) |
| 141 | #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) |
| 142 | |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 143 | #define U3P_U3_PHYD_LFPS1 0x00c |
| 144 | #define P3D_RG_FWAKE_TH GENMASK(21, 16) |
| 145 | #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) |
| 146 | |
| 147 | #define U3P_U3_PHYD_CDR1 0x05c |
| 148 | #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) |
| 149 | #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) |
| 150 | #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) |
| 151 | #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) |
| 152 | |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 153 | #define U3P_U3_PHYD_RXDET1 0x128 |
| 154 | #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) |
| 155 | #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) |
| 156 | |
| 157 | #define U3P_U3_PHYD_RXDET2 0x12c |
| 158 | #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) |
| 159 | #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) |
| 160 | |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 161 | #define U3P_SPLLC_XTALCTL3 0x018 |
| 162 | #define XC3_RG_U3_XTAL_RX_PWD BIT(9) |
| 163 | #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) |
| 164 | |
| 165 | struct u2phy_banks { |
| 166 | void __iomem *misc; |
| 167 | void __iomem *fmreg; |
| 168 | void __iomem *com; |
| 169 | }; |
| 170 | |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 171 | struct u3phy_banks { |
| 172 | void __iomem *spllc; |
| 173 | void __iomem *chip; |
| 174 | void __iomem *phyd; /* include u3phyd_bank2 */ |
| 175 | void __iomem *phya; /* include u3phya_da */ |
| 176 | }; |
| 177 | |
| 178 | struct mtk_phy_instance { |
| 179 | void __iomem *port_base; |
| 180 | const struct device_node *np; |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 181 | union { |
| 182 | struct u2phy_banks u2_banks; |
| 183 | struct u3phy_banks u3_banks; |
| 184 | }; |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 185 | |
| 186 | /* reference clock of anolog phy */ |
| 187 | struct clk ref_clk; |
| 188 | u32 index; |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 189 | u32 type; |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 190 | }; |
| 191 | |
| 192 | struct mtk_tphy { |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 193 | struct udevice *dev; |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 194 | void __iomem *sif_base; |
| 195 | struct mtk_phy_instance **phys; |
| 196 | int nphys; |
| 197 | }; |
| 198 | |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 199 | static void u2_phy_instance_init(struct mtk_tphy *tphy, |
| 200 | struct mtk_phy_instance *instance) |
| 201 | { |
| 202 | struct u2phy_banks *u2_banks = &instance->u2_banks; |
| 203 | |
| 204 | /* switch to USB function, and enable usb pll */ |
| 205 | clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0, |
| 206 | P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM, |
| 207 | P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0)); |
| 208 | |
| 209 | clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN); |
| 210 | setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN); |
| 211 | |
| 212 | /* disable switch 100uA current to SSUSB */ |
| 213 | clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN); |
| 214 | |
| 215 | clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK); |
| 216 | |
| 217 | /* DP/DM BC1.1 path Disable */ |
| 218 | clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6, |
| 219 | PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH, |
| 220 | PA6_RG_U2_SQTH_VAL(2)); |
| 221 | |
| 222 | /* set HS slew rate */ |
| 223 | clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5, |
| 224 | PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); |
| 225 | |
| 226 | dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); |
| 227 | } |
| 228 | |
| 229 | static void u2_phy_instance_power_on(struct mtk_tphy *tphy, |
| 230 | struct mtk_phy_instance *instance) |
| 231 | { |
| 232 | struct u2phy_banks *u2_banks = &instance->u2_banks; |
| 233 | |
| 234 | clrbits_le32(u2_banks->com + U3P_U2PHYDTM0, |
| 235 | P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); |
| 236 | |
| 237 | /* OTG Enable */ |
| 238 | setbits_le32(u2_banks->com + U3P_USBPHYACR6, |
| 239 | PA6_RG_U2_OTG_VBUSCMP_EN); |
| 240 | |
| 241 | clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1, |
| 242 | P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID); |
| 243 | |
| 244 | dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); |
| 245 | } |
| 246 | |
| 247 | static void u2_phy_instance_power_off(struct mtk_tphy *tphy, |
| 248 | struct mtk_phy_instance *instance) |
| 249 | { |
| 250 | struct u2phy_banks *u2_banks = &instance->u2_banks; |
| 251 | |
| 252 | clrbits_le32(u2_banks->com + U3P_U2PHYDTM0, |
| 253 | P2C_RG_XCVRSEL | P2C_RG_DATAIN); |
| 254 | |
| 255 | /* OTG Disable */ |
| 256 | clrbits_le32(u2_banks->com + U3P_USBPHYACR6, |
| 257 | PA6_RG_U2_OTG_VBUSCMP_EN); |
| 258 | |
| 259 | clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1, |
| 260 | P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND); |
| 261 | |
| 262 | dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); |
| 263 | } |
| 264 | |
| 265 | static void u3_phy_instance_init(struct mtk_tphy *tphy, |
| 266 | struct mtk_phy_instance *instance) |
| 267 | { |
| 268 | struct u3phy_banks *u3_banks = &instance->u3_banks; |
| 269 | |
| 270 | /* gating PCIe Analog XTAL clock */ |
| 271 | setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3, |
| 272 | XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD); |
| 273 | |
| 274 | /* gating XSQ */ |
| 275 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0, |
| 276 | P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2)); |
| 277 | |
| 278 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9, |
| 279 | P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4)); |
| 280 | |
| 281 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6, |
| 282 | P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe)); |
| 283 | |
| 284 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1, |
| 285 | P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1, |
| 286 | P3D_RG_CDR_BIR_LTD0_VAL(0xc) | |
| 287 | P3D_RG_CDR_BIR_LTD1_VAL(0x3)); |
| 288 | |
| 289 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1, |
| 290 | P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34)); |
| 291 | |
| 292 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1, |
| 293 | P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10)); |
| 294 | |
| 295 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2, |
| 296 | P3D_RG_RXDET_STB2_SET_P3, |
| 297 | P3D_RG_RXDET_STB2_SET_P3_VAL(0x10)); |
| 298 | |
| 299 | dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); |
| 300 | } |
| 301 | |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 302 | static void pcie_phy_instance_init(struct mtk_tphy *tphy, |
| 303 | struct mtk_phy_instance *instance) |
| 304 | { |
| 305 | struct u3phy_banks *u3_banks = &instance->u3_banks; |
| 306 | |
| 307 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0, |
| 308 | P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, |
| 309 | P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | |
| 310 | P3A_RG_XTAL_EXT_PE2H_VAL(0x2)); |
| 311 | |
| 312 | /* ref clk drive */ |
| 313 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, |
| 314 | P3A_RG_CLKDRV_AMP_VAL(0x4)); |
| 315 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, |
| 316 | P3A_RG_CLKDRV_OFF_VAL(0x1)); |
| 317 | |
| 318 | /* SSC delta -5000ppm */ |
| 319 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20, |
| 320 | P3A_RG_PLL_DELTA1_PE2H, |
| 321 | P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c)); |
| 322 | |
| 323 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25, |
| 324 | P3A_RG_PLL_DELTA_PE2H, |
| 325 | P3A_RG_PLL_DELTA_PE2H_VAL(0x36)); |
| 326 | |
| 327 | /* change pll BW 0.6M */ |
| 328 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5, |
| 329 | P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H, |
| 330 | P3A_RG_PLL_BR_PE2H_VAL(0x1) | |
| 331 | P3A_RG_PLL_IC_PE2H_VAL(0x1)); |
| 332 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4, |
| 333 | P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H, |
| 334 | P3A_RG_PLL_BC_PE2H_VAL(0x3)); |
| 335 | |
| 336 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6, |
| 337 | P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2)); |
| 338 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7, |
| 339 | P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa)); |
| 340 | |
| 341 | /* Tx Detect Rx Timing: 10us -> 5us */ |
| 342 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1, |
| 343 | P3D_RG_RXDET_STB2_SET, |
| 344 | P3D_RG_RXDET_STB2_SET_VAL(0x10)); |
| 345 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2, |
| 346 | P3D_RG_RXDET_STB2_SET_P3, |
| 347 | P3D_RG_RXDET_STB2_SET_P3_VAL(0x10)); |
| 348 | |
| 349 | /* wait for PCIe subsys register to active */ |
| 350 | udelay(3000); |
| 351 | } |
| 352 | |
| 353 | static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, |
| 354 | struct mtk_phy_instance *instance) |
| 355 | { |
| 356 | struct u3phy_banks *bank = &instance->u3_banks; |
| 357 | |
| 358 | clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD, |
| 359 | P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); |
| 360 | clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE, |
| 361 | P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); |
| 362 | } |
| 363 | |
| 364 | static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, |
| 365 | struct mtk_phy_instance *instance) |
| 366 | |
| 367 | { |
| 368 | struct u3phy_banks *bank = &instance->u3_banks; |
| 369 | |
| 370 | setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD, |
| 371 | P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); |
| 372 | setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE, |
| 373 | P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); |
| 374 | } |
| 375 | |
| 376 | static void phy_v1_banks_init(struct mtk_tphy *tphy, |
| 377 | struct mtk_phy_instance *instance) |
| 378 | { |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 379 | struct u2phy_banks *u2_banks = &instance->u2_banks; |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 380 | struct u3phy_banks *u3_banks = &instance->u3_banks; |
| 381 | |
| 382 | switch (instance->type) { |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 383 | case PHY_TYPE_USB2: |
| 384 | u2_banks->misc = NULL; |
| 385 | u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; |
| 386 | u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; |
| 387 | break; |
| 388 | case PHY_TYPE_USB3: |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 389 | case PHY_TYPE_PCIE: |
| 390 | u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; |
| 391 | u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; |
| 392 | u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; |
| 393 | u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; |
| 394 | break; |
| 395 | default: |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 396 | dev_err(tphy->dev, "incompatible PHY type\n"); |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 397 | return; |
| 398 | } |
| 399 | } |
| 400 | |
| 401 | static int mtk_phy_init(struct phy *phy) |
| 402 | { |
| 403 | struct mtk_tphy *tphy = dev_get_priv(phy->dev); |
| 404 | struct mtk_phy_instance *instance = tphy->phys[phy->id]; |
| 405 | int ret; |
| 406 | |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 407 | ret = clk_enable(&instance->ref_clk); |
Chunfeng Yun | 3b6351a | 2020-01-09 11:35:09 +0800 | [diff] [blame] | 408 | if (ret) |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 409 | return ret; |
| 410 | |
| 411 | switch (instance->type) { |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 412 | case PHY_TYPE_USB2: |
| 413 | u2_phy_instance_init(tphy, instance); |
| 414 | break; |
| 415 | case PHY_TYPE_USB3: |
| 416 | u3_phy_instance_init(tphy, instance); |
| 417 | break; |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 418 | case PHY_TYPE_PCIE: |
| 419 | pcie_phy_instance_init(tphy, instance); |
| 420 | break; |
| 421 | default: |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 422 | dev_err(tphy->dev, "incompatible PHY type\n"); |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 423 | return -EINVAL; |
| 424 | } |
| 425 | |
| 426 | return 0; |
| 427 | } |
| 428 | |
| 429 | static int mtk_phy_power_on(struct phy *phy) |
| 430 | { |
| 431 | struct mtk_tphy *tphy = dev_get_priv(phy->dev); |
| 432 | struct mtk_phy_instance *instance = tphy->phys[phy->id]; |
| 433 | |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 434 | if (instance->type == PHY_TYPE_USB2) |
| 435 | u2_phy_instance_power_on(tphy, instance); |
| 436 | else if (instance->type == PHY_TYPE_PCIE) |
| 437 | pcie_phy_instance_power_on(tphy, instance); |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 438 | |
| 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | static int mtk_phy_power_off(struct phy *phy) |
| 443 | { |
| 444 | struct mtk_tphy *tphy = dev_get_priv(phy->dev); |
| 445 | struct mtk_phy_instance *instance = tphy->phys[phy->id]; |
| 446 | |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 447 | if (instance->type == PHY_TYPE_USB2) |
| 448 | u2_phy_instance_power_off(tphy, instance); |
| 449 | else if (instance->type == PHY_TYPE_PCIE) |
| 450 | pcie_phy_instance_power_off(tphy, instance); |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 451 | |
| 452 | return 0; |
| 453 | } |
| 454 | |
| 455 | static int mtk_phy_exit(struct phy *phy) |
| 456 | { |
| 457 | struct mtk_tphy *tphy = dev_get_priv(phy->dev); |
| 458 | struct mtk_phy_instance *instance = tphy->phys[phy->id]; |
| 459 | |
| 460 | clk_disable(&instance->ref_clk); |
| 461 | |
| 462 | return 0; |
| 463 | } |
| 464 | |
| 465 | static int mtk_phy_xlate(struct phy *phy, |
| 466 | struct ofnode_phandle_args *args) |
| 467 | { |
| 468 | struct mtk_tphy *tphy = dev_get_priv(phy->dev); |
| 469 | struct mtk_phy_instance *instance = NULL; |
| 470 | const struct device_node *phy_np = ofnode_to_np(args->node); |
| 471 | u32 index; |
| 472 | |
| 473 | if (!phy_np) { |
| 474 | dev_err(phy->dev, "null pointer phy node\n"); |
| 475 | return -EINVAL; |
| 476 | } |
| 477 | |
| 478 | if (args->args_count < 1) { |
| 479 | dev_err(phy->dev, "invalid number of cells in 'phy' property\n"); |
| 480 | return -EINVAL; |
| 481 | } |
| 482 | |
| 483 | for (index = 0; index < tphy->nphys; index++) |
| 484 | if (phy_np == tphy->phys[index]->np) { |
| 485 | instance = tphy->phys[index]; |
| 486 | break; |
| 487 | } |
| 488 | |
| 489 | if (!instance) { |
| 490 | dev_err(phy->dev, "failed to find appropriate phy\n"); |
| 491 | return -EINVAL; |
| 492 | } |
| 493 | |
| 494 | phy->id = index; |
| 495 | instance->type = args->args[1]; |
| 496 | if (!(instance->type == PHY_TYPE_USB2 || |
| 497 | instance->type == PHY_TYPE_USB3 || |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 498 | instance->type == PHY_TYPE_PCIE)) { |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 499 | dev_err(phy->dev, "unsupported device type\n"); |
| 500 | return -EINVAL; |
| 501 | } |
| 502 | |
| 503 | phy_v1_banks_init(tphy, instance); |
| 504 | |
| 505 | return 0; |
| 506 | } |
| 507 | |
| 508 | static const struct phy_ops mtk_tphy_ops = { |
| 509 | .init = mtk_phy_init, |
| 510 | .exit = mtk_phy_exit, |
| 511 | .power_on = mtk_phy_power_on, |
| 512 | .power_off = mtk_phy_power_off, |
| 513 | .of_xlate = mtk_phy_xlate, |
| 514 | }; |
| 515 | |
| 516 | static int mtk_tphy_probe(struct udevice *dev) |
| 517 | { |
| 518 | struct mtk_tphy *tphy = dev_get_priv(dev); |
| 519 | ofnode subnode; |
| 520 | int index = 0; |
| 521 | |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 522 | tphy->nphys = dev_get_child_count(dev); |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 523 | |
| 524 | tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys), |
| 525 | GFP_KERNEL); |
| 526 | if (!tphy->phys) |
| 527 | return -ENOMEM; |
| 528 | |
Chunfeng Yun | ee6eabb | 2020-05-02 11:35:15 +0200 | [diff] [blame^] | 529 | tphy->dev = dev; |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 530 | tphy->sif_base = dev_read_addr_ptr(dev); |
| 531 | if (!tphy->sif_base) |
| 532 | return -ENOENT; |
| 533 | |
| 534 | dev_for_each_subnode(subnode, dev) { |
| 535 | struct mtk_phy_instance *instance; |
| 536 | fdt_addr_t addr; |
| 537 | int err; |
| 538 | |
| 539 | instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); |
| 540 | if (!instance) |
| 541 | return -ENOMEM; |
| 542 | |
| 543 | addr = ofnode_get_addr(subnode); |
| 544 | if (addr == FDT_ADDR_T_NONE) |
| 545 | return -ENOMEM; |
| 546 | |
| 547 | instance->port_base = map_sysmem(addr, 0); |
| 548 | instance->index = index; |
| 549 | instance->np = ofnode_to_np(subnode); |
| 550 | tphy->phys[index] = instance; |
| 551 | index++; |
| 552 | |
Chunfeng Yun | ce0069e | 2020-01-09 11:35:10 +0800 | [diff] [blame] | 553 | err = clk_get_optional_nodev(subnode, "ref", |
| 554 | &instance->ref_clk); |
Ryder Lee | 235bad0 | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 555 | if (err) |
| 556 | return err; |
| 557 | } |
| 558 | |
| 559 | return 0; |
| 560 | } |
| 561 | |
| 562 | static const struct udevice_id mtk_tphy_id_table[] = { |
| 563 | { .compatible = "mediatek,generic-tphy-v1", }, |
| 564 | { } |
| 565 | }; |
| 566 | |
| 567 | U_BOOT_DRIVER(mtk_tphy) = { |
| 568 | .name = "mtk-tphy", |
| 569 | .id = UCLASS_PHY, |
| 570 | .of_match = mtk_tphy_id_table, |
| 571 | .ops = &mtk_tphy_ops, |
| 572 | .probe = mtk_tphy_probe, |
| 573 | .priv_auto_alloc_size = sizeof(struct mtk_tphy), |
| 574 | }; |