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Michal Simek194846f2012-09-14 00:55:24 +00001/*
2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Michal Simek194846f2012-09-14 00:55:24 +00006 */
7
Michal Simek59da82e2016-07-14 14:40:03 +02008#include <clk.h>
Michal Simek194846f2012-09-14 00:55:24 +00009#include <common.h>
Simon Glass42800ff2015-10-17 19:41:27 -060010#include <debug_uart.h>
11#include <dm.h>
Simon Glassc54c0a42015-10-17 19:41:22 -060012#include <errno.h>
Michal Simekc9416b92014-02-24 11:16:33 +010013#include <fdtdec.h>
Michal Simek194846f2012-09-14 00:55:24 +000014#include <watchdog.h>
15#include <asm/io.h>
16#include <linux/compiler.h>
17#include <serial.h>
Michal Simekbf834952013-12-19 23:38:58 +053018#include <asm/arch/hardware.h>
Michal Simek194846f2012-09-14 00:55:24 +000019
Michal Simekc9416b92014-02-24 11:16:33 +010020DECLARE_GLOBAL_DATA_PTR;
21
Michal Simek6cd0f2a2016-02-03 15:16:51 +010022#define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */
Simon Glass42800ff2015-10-17 19:41:27 -060023#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
Michal Simek194846f2012-09-14 00:55:24 +000024#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
25
26#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
27#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */
28#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */
29#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */
30
31#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
32
Michal Simek194846f2012-09-14 00:55:24 +000033struct uart_zynq {
Michal Simeka2425e62015-01-07 15:00:47 +010034 u32 control; /* 0x0 - Control Register [8:0] */
35 u32 mode; /* 0x4 - Mode Register [10:0] */
Michal Simek194846f2012-09-14 00:55:24 +000036 u32 reserved1[4];
Michal Simeka2425e62015-01-07 15:00:47 +010037 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
Michal Simek194846f2012-09-14 00:55:24 +000038 u32 reserved2[4];
Michal Simeka2425e62015-01-07 15:00:47 +010039 u32 channel_sts; /* 0x2c - Channel Status [11:0] */
40 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
41 u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
Michal Simek194846f2012-09-14 00:55:24 +000042};
43
Simon Glass42800ff2015-10-17 19:41:27 -060044struct zynq_uart_priv {
45 struct uart_zynq *regs;
Michal Simek194846f2012-09-14 00:55:24 +000046};
47
Michal Simek194846f2012-09-14 00:55:24 +000048/* Set up the baud rate in gd struct */
Simon Glassc54c0a42015-10-17 19:41:22 -060049static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
50 unsigned long clock, unsigned long baud)
Michal Simek194846f2012-09-14 00:55:24 +000051{
52 /* Calculation results. */
53 unsigned int calc_bauderror, bdiv, bgen;
54 unsigned long calc_baud = 0;
Michal Simek194846f2012-09-14 00:55:24 +000055
Michal Simek04bc5c92015-04-15 13:05:06 +020056 /* Covering case where input clock is so slow */
Simon Glassc54c0a42015-10-17 19:41:22 -060057 if (clock < 1000000 && baud > 4800)
58 baud = 4800;
Michal Simek04bc5c92015-04-15 13:05:06 +020059
Michal Simek194846f2012-09-14 00:55:24 +000060 /* master clock
61 * Baud rate = ------------------
62 * bgen * (bdiv + 1)
63 *
64 * Find acceptable values for baud generation.
65 */
66 for (bdiv = 4; bdiv < 255; bdiv++) {
67 bgen = clock / (baud * (bdiv + 1));
68 if (bgen < 2 || bgen > 65535)
69 continue;
70
71 calc_baud = clock / (bgen * (bdiv + 1));
72
73 /*
74 * Use first calculated baudrate with
75 * an acceptable (<3%) error
76 */
77 if (baud > calc_baud)
78 calc_bauderror = baud - calc_baud;
79 else
80 calc_bauderror = calc_baud - baud;
81 if (((calc_bauderror * 100) / baud) < 3)
82 break;
83 }
84
85 writel(bdiv, &regs->baud_rate_divider);
86 writel(bgen, &regs->baud_rate_gen);
87}
88
Simon Glassc54c0a42015-10-17 19:41:22 -060089/* Initialize the UART, with...some settings. */
90static void _uart_zynq_serial_init(struct uart_zynq *regs)
91{
92 /* RX/TX enabled & reset */
93 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
94 ZYNQ_UART_CR_RXRST, &regs->control);
95 writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
96}
97
Simon Glassc54c0a42015-10-17 19:41:22 -060098static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
99{
Michal Simek6cd0f2a2016-02-03 15:16:51 +0100100 if (!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
Simon Glassc54c0a42015-10-17 19:41:22 -0600101 return -EAGAIN;
102
103 writel(c, &regs->tx_rx_fifo);
104
105 return 0;
106}
107
Simon Glass42800ff2015-10-17 19:41:27 -0600108int zynq_serial_setbrg(struct udevice *dev, int baudrate)
Michal Simek194846f2012-09-14 00:55:24 +0000109{
Simon Glass42800ff2015-10-17 19:41:27 -0600110 struct zynq_uart_priv *priv = dev_get_priv(dev);
Michal Simek59da82e2016-07-14 14:40:03 +0200111 unsigned long clock;
Michal Simek194846f2012-09-14 00:55:24 +0000112
Michal Simek59da82e2016-07-14 14:40:03 +0200113 int ret;
114 struct clk clk;
115
116 ret = clk_get_by_index(dev, 0, &clk);
117 if (ret < 0) {
118 dev_err(dev, "failed to get clock\n");
119 return ret;
120 }
121
122 clock = clk_get_rate(&clk);
123 if (IS_ERR_VALUE(clock)) {
124 dev_err(dev, "failed to get rate\n");
125 return clock;
126 }
127 debug("%s: CLK %ld\n", __func__, clock);
128
129 ret = clk_enable(&clk);
130 if (ret && ret != -ENOSYS) {
131 dev_err(dev, "failed to enable clock\n");
132 return ret;
133 }
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +0100134
Simon Glass42800ff2015-10-17 19:41:27 -0600135 _uart_zynq_serial_setbrg(priv->regs, clock, baudrate);
Michal Simek194846f2012-09-14 00:55:24 +0000136
Simon Glass42800ff2015-10-17 19:41:27 -0600137 return 0;
Michal Simek194846f2012-09-14 00:55:24 +0000138}
139
Simon Glass42800ff2015-10-17 19:41:27 -0600140static int zynq_serial_probe(struct udevice *dev)
Michal Simek194846f2012-09-14 00:55:24 +0000141{
Simon Glass42800ff2015-10-17 19:41:27 -0600142 struct zynq_uart_priv *priv = dev_get_priv(dev);
143
144 _uart_zynq_serial_init(priv->regs);
145
146 return 0;
Michal Simek194846f2012-09-14 00:55:24 +0000147}
148
Simon Glass42800ff2015-10-17 19:41:27 -0600149static int zynq_serial_getc(struct udevice *dev)
Michal Simek194846f2012-09-14 00:55:24 +0000150{
Simon Glass42800ff2015-10-17 19:41:27 -0600151 struct zynq_uart_priv *priv = dev_get_priv(dev);
152 struct uart_zynq *regs = priv->regs;
Michal Simek194846f2012-09-14 00:55:24 +0000153
Simon Glass42800ff2015-10-17 19:41:27 -0600154 if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
155 return -EAGAIN;
Michal Simek194846f2012-09-14 00:55:24 +0000156
Michal Simek194846f2012-09-14 00:55:24 +0000157 return readl(&regs->tx_rx_fifo);
158}
159
Simon Glass42800ff2015-10-17 19:41:27 -0600160static int zynq_serial_putc(struct udevice *dev, const char ch)
Michal Simekc9416b92014-02-24 11:16:33 +0100161{
Simon Glass42800ff2015-10-17 19:41:27 -0600162 struct zynq_uart_priv *priv = dev_get_priv(dev);
Michal Simekc9416b92014-02-24 11:16:33 +0100163
Simon Glass42800ff2015-10-17 19:41:27 -0600164 return _uart_zynq_serial_putc(priv->regs, ch);
Michal Simekc9416b92014-02-24 11:16:33 +0100165}
Tom Rini51d81022012-10-08 14:46:23 -0700166
Simon Glass42800ff2015-10-17 19:41:27 -0600167static int zynq_serial_pending(struct udevice *dev, bool input)
Tom Rini51d81022012-10-08 14:46:23 -0700168{
Simon Glass42800ff2015-10-17 19:41:27 -0600169 struct zynq_uart_priv *priv = dev_get_priv(dev);
170 struct uart_zynq *regs = priv->regs;
171
172 if (input)
173 return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
174 else
175 return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
Tom Rini51d81022012-10-08 14:46:23 -0700176}
Simon Glassc54c0a42015-10-17 19:41:22 -0600177
Simon Glass42800ff2015-10-17 19:41:27 -0600178static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
179{
180 struct zynq_uart_priv *priv = dev_get_priv(dev);
Simon Glass42800ff2015-10-17 19:41:27 -0600181
Simon Glassa821c4a2017-05-17 17:18:05 -0600182 priv->regs = (struct uart_zynq *)devfdt_get_addr(dev);
Simon Glass42800ff2015-10-17 19:41:27 -0600183
184 return 0;
185}
186
187static const struct dm_serial_ops zynq_serial_ops = {
188 .putc = zynq_serial_putc,
189 .pending = zynq_serial_pending,
190 .getc = zynq_serial_getc,
191 .setbrg = zynq_serial_setbrg,
192};
193
194static const struct udevice_id zynq_serial_ids[] = {
195 { .compatible = "xlnx,xuartps" },
196 { .compatible = "cdns,uart-r1p8" },
Michal Simeka2533182016-01-14 11:45:52 +0100197 { .compatible = "cdns,uart-r1p12" },
Simon Glass42800ff2015-10-17 19:41:27 -0600198 { }
199};
200
Michal Simek6bf87da2015-12-01 14:29:34 +0100201U_BOOT_DRIVER(serial_zynq) = {
Simon Glass42800ff2015-10-17 19:41:27 -0600202 .name = "serial_zynq",
203 .id = UCLASS_SERIAL,
204 .of_match = zynq_serial_ids,
205 .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
206 .priv_auto_alloc_size = sizeof(struct zynq_uart_priv),
207 .probe = zynq_serial_probe,
208 .ops = &zynq_serial_ops,
209 .flags = DM_FLAG_PRE_RELOC,
210};
211
Simon Glassc54c0a42015-10-17 19:41:22 -0600212#ifdef CONFIG_DEBUG_UART_ZYNQ
Michal Simek80dc9992016-01-05 12:49:21 +0100213static inline void _debug_uart_init(void)
Simon Glassc54c0a42015-10-17 19:41:22 -0600214{
215 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
216
217 _uart_zynq_serial_init(regs);
218 _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
219 CONFIG_BAUDRATE);
220}
221
222static inline void _debug_uart_putc(int ch)
223{
224 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
225
226 while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
227 WATCHDOG_RESET();
228}
229
230DEBUG_UART_FUNCS
231
232#endif