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wdenkc6097192002-11-03 00:24:07 +00001 /*
2 * (C) Copyright 2001
3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24#ifndef _PCI_PARTS_H_
25#define _PCI_PARTS_H_
26
27
28/* Board specific file containing:
29 * - PCI Memory Mapping
30 * - PCI IO Mapping
31 * - PCI Interrupt Mapping
32 */
33
34/* PIP405 PCI INT Routing:
35 * IRQ0 VECTOR
36 * PIXX4 IDSEL = AD16 INTA# 28 (Function 2 USB is INTD# = 31)
37 * VGA IDSEL = AD17 INTB# 29
38 * SCSI IDSEL = AD18 INTC# 30
39 * PC104 IDSEL0 = AD20 INTA# 28
40 * PC104 IDSEL1 = AD21 INTB# 29
41 * PC104 IDSEL2 = AD22 INTC# 30
42 * PC104 IDSEL3 = AD23 INTD# 31
43 *
44 * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00
45 * ^ ^ ^ ^ ^
46 * 31 23 15 10 7
47 * E = Enabled
48 * B = Bussnumber
49 * D = Devicenumber (Device0 = AD10)
50 * F = Functionnumber
51 * R = Registernumber
52 *
53 * Device = (busdevfunc>>11) + 10
54 * Vector = devicenumber % 4 + 28
55 *
56 */
57#define PCI_HIGHEST_ON_BOARD_ID 19
58/*#define PCI_DEV_NUMBER(x) (((x>>11) & 0x1f) + 10) */
59#define PCI_IRQ_VECTOR(x) ((PCI_DEV(x) + 10) % 4) + 28
60
61
wdenkc6097192002-11-03 00:24:07 +000062/* PCI Device List for PIP405 */
63
64/* Mapping:
65 * +-------------+------------+------------+--------------------------------+
66 * ¦ PCI MemAddr | PCI IOAddr | Local Addr | Device / Function |
67 * +-------------+------------+------------+--------------------------------+
68 * | 0x00000000 | | 0xA0000000 | ISA Memory (hard wired) |
69 * | 0x00FFFFFF | | 0xA0FFFFFF | |
70 * +-------------+------------+------------+--------------------------------+
71 * | | 0x00000000 | 0xE8000000 | ISA IO (hard wired) |
72 * | | 0x0000FFFF | 0xE800FFFF | |
73 * +-------------+------------+------------+--------------------------------+
74 * | 0x80000000 | | 0x80000000 | VGA Controller Memory |
75 * | 0x80FFFFFF | | 0x80FFFFFF | |
76 * +-------------+------------+------------+--------------------------------+
77 * | 0x81000000 | | 0x81000000 | SCSI Controller Memory |
78 * | 0x81FFFFFF | | 0x81FFFFFF | |
79 * +-------------+------------+------------+--------------------------------+
80 */
81
82struct pci_pip405_config_entry {
83 int index; /* address */
84 unsigned long val; /* value */
85 int width; /* data size */
86};
87
88extern void pci_pip405_write_regs(struct pci_controller *,
89 pci_dev_t,
90 struct pci_config_table *);
91
92/* PIIX4 ISA Bridge Function 0 */
93static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
94 {PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */
wdenk7205e402003-09-10 22:30:53 +000095 {PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */
wdenkc6097192002-11-03 00:24:07 +000096 {PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */
97 {PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */
98 {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */
99#if defined(CONFIG_PIP405)
100 {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */
101 {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */
102#endif
103 {PCI_CFG_PIIX4_DLC, 0x0, 1}, /* disable passive release feature */
104 { } /* end of device table */
105};
106
107/* PIIX4 IDE Controller Function 1 */
108static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
wdenk7205e402003-09-10 22:30:53 +0000109 {PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */
wdenkc6097192002-11-03 00:24:07 +0000110 {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
wdenkf3e0de62003-06-04 15:05:30 +0000111#if !defined(CONFIG_MIP405T)
wdenkc6097192002-11-03 00:24:07 +0000112 {PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
wdenkf3e0de62003-06-04 15:05:30 +0000113#else
wdenk27b207f2003-07-24 23:38:38 +0000114 {PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */
wdenkf3e0de62003-06-04 15:05:30 +0000115#endif
wdenkc6097192002-11-03 00:24:07 +0000116 { } /* end of device table */
117};
118
119/* PIIX4 USB Controller Function 2 */
120static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
wdenkf3e0de62003-06-04 15:05:30 +0000121#if !defined(CONFIG_MIP405T)
wdenkc6097192002-11-03 00:24:07 +0000122 {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */
123 {PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */
124 {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */
125 {0xC0, 0x2000, 2}, /* Legacy support */
126 {PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */
wdenkf3e0de62003-06-04 15:05:30 +0000127#endif
wdenkc6097192002-11-03 00:24:07 +0000128 { } /* end of device table */
129};
130
131/* PIIX4 Power Management Function 3 */
132static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
wdenk7205e402003-09-10 22:30:53 +0000133 {PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */
wdenkc6097192002-11-03 00:24:07 +0000134 {PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */
wdenk7205e402003-09-10 22:30:53 +0000135 {PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */
136 {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
wdenkc6097192002-11-03 00:24:07 +0000137 { } /* end of device table */
138};
139/* PPC405 Dummy only used to prevent autosetup on this host bridge */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200140static struct pci_pip405_config_entry ppc405_dummy[] = {
wdenkc6097192002-11-03 00:24:07 +0000141 { } /* end of device table */
142};
143
144void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
145 struct pci_config_table *entry);
146
147
148static struct pci_config_table pci_pip405_config_table[]={
149 {PCI_VENDOR_ID_IBM, /* 405 dummy */
150 PCI_DEVICE_ID_IBM_405GP,
151 PCI_ANY_ID,
152 PCI_ANY_ID, PCI_ANY_ID, 0,
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200153 pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
wdenkc6097192002-11-03 00:24:07 +0000154
155 {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */
156 PCI_DEVICE_ID_INTEL_82371AB_0,
157 PCI_ANY_ID,
158 PCI_ANY_ID, PCI_ANY_ID, 0,
159 pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}},
160
161 {PCI_VENDOR_ID_INTEL, /* PIIX4 IDE Controller Function 1 */
162 PCI_DEVICE_ID_INTEL_82371AB,
163 PCI_ANY_ID,
164 PCI_ANY_ID, PCI_ANY_ID, 1,
165 pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}},
166
167 {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 2 */
168 PCI_DEVICE_ID_INTEL_82371AB_2,
169 PCI_ANY_ID,
170 PCI_ANY_ID, PCI_ANY_ID, 2,
171 pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}},
172
173 {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 3 */
174 PCI_DEVICE_ID_INTEL_82371AB_3,
175 PCI_ANY_ID,
176 PCI_ANY_ID, PCI_ANY_ID, 3,
177 pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}},
178
179 {PCI_ANY_ID,
180 PCI_ANY_ID,
181 PCI_CLASS_DISPLAY_VGA,
182 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
183 pci_405gp_setup_vga},
184
185 {PCI_ANY_ID,
186 PCI_ANY_ID,
187 PCI_CLASS_NOT_DEFINED_VGA,
188 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
189 pci_405gp_setup_vga},
190
191 { }
192};
193#endif /* _PCI_PARTS_H_ */