blob: 2c847d08a46505f26a6a0356fde39fa4f6f2cb95 [file] [log] [blame]
Stefan Roesec0340752008-11-12 13:30:10 +01001/*
2 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#include <config.h>
21#include <common.h>
22#include <asm/io.h>
23
24#define UART_1_BASE 0xBF89C000
25
26#define UART_RBR_OFF 0x00 /* receiver buffer reg */
27#define UART_THR_OFF 0x00 /* transmit holding reg */
28#define UART_DLL_OFF 0x00 /* divisor latch low reg */
29#define UART_IER_OFF 0x04 /* interrupt enable reg */
30#define UART_DLH_OFF 0x04 /* receiver buffer reg */
31#define UART_FCR_OFF 0x08 /* fifo control register */
32#define UART_LCR_OFF 0x0c /* line control register */
33#define UART_MCR_OFF 0x10 /* modem control register */
34#define UART_LSR_OFF 0x14 /* line status register */
35#define UART_MSR_OFF 0x18 /* modem status register */
36#define UART_SCR_OFF 0x1c /* scratch pad register */
37
38#define UART_RCV_DATA_RDY 0x01 /* Data Received */
39#define UART_XMT_HOLD_EMPTY 0x20
40#define UART_TRANSMIT_EMPTY 0x40
41
42/* 7 bit on line control reg. enalbing rw to dll and dlh */
43#define UART_LCR_DLAB 0x0080
44
45#define UART___9600_BDR 0x84
46#define UART__19200_BDR 0x42
47#define UART_115200_BDR 0x08
48
49#define UART_DIS_ALL_INTER 0x00 /* disable all interrupts */
50
51#define UART_5DATA_BITS 0x0000 /* 5 [bits] 1.5 bits 2 */
52#define UART_6DATA_BITS 0x0001 /* 6 [bits] 1 bits 2 */
53#define UART_7DATA_BITS 0x0002 /* 7 [bits] 1 bits 2 */
54#define UART_8DATA_BITS 0x0003 /* 8 [bits] 1 bits 2 */
55
56static void vcth_uart_set_baud_rate(u32 address, u32 dh, u32 dl)
57{
58 u32 val = __raw_readl(UART_1_BASE + UART_LCR_OFF);
59
60 /* set 7 bit on 1 */
61 val |= UART_LCR_DLAB;
62 __raw_writel(val, UART_1_BASE + UART_LCR_OFF);
63
64 __raw_writel(dl, UART_1_BASE + UART_DLL_OFF);
65 __raw_writel(dh, UART_1_BASE + UART_DLH_OFF);
66
67 /* set 7 bit on 0 */
68 val &= ~UART_LCR_DLAB;
69 __raw_writel(val, UART_1_BASE + UART_LCR_OFF);
70
71 return;
72}
73
74int serial_init(void)
75{
76 __raw_writel(UART_DIS_ALL_INTER, UART_1_BASE + UART_IER_OFF);
77 vcth_uart_set_baud_rate(UART_1_BASE, 0, UART_115200_BDR);
78 __raw_writel(UART_8DATA_BITS, UART_1_BASE + UART_LCR_OFF);
79
80 return 0;
81}
82
83void serial_setbrg(void)
84{
85 /*
86 * Baudrate change not supported currently, fixed to 115200 baud
87 */
88}
89
90void serial_putc(const char c)
91{
92 if (c == '\n')
93 serial_putc('\r');
94
95 while (!(UART_XMT_HOLD_EMPTY & __raw_readl(UART_1_BASE + UART_LSR_OFF)))
96 ;
97
98 __raw_writel(c, UART_1_BASE + UART_THR_OFF);
99}
100
101void serial_puts(const char *s)
102{
103 while (*s)
104 serial_putc(*s++);
105}
106
107int serial_getc(void)
108{
109 while (!(UART_RCV_DATA_RDY & __raw_readl(UART_1_BASE + UART_LSR_OFF)))
110 ;
111
112 return __raw_readl(UART_1_BASE + UART_RBR_OFF) & 0xff;
113}
114
115int serial_tstc(void)
116{
117 if (!(UART_RCV_DATA_RDY & __raw_readl(UART_1_BASE + UART_LSR_OFF)))
118 return 0;
119
120 return 1;
121}