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Macpaul Lin0f3864a2011-09-27 15:31:07 +08001/*
2 * (C) Copyright 2011 Andes Technology Corp
3 * Macpaul Lin <macpaul@andestech.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20/*
21 * Andes Power Control Unit
22 */
23#ifndef __ANDES_PCU_H
24#define __ANDES_PCU_H
25
26#ifndef __ASSEMBLY__
27
28struct pcs {
29 unsigned int cr; /* PCSx Configuration (clock scaling) */
30 unsigned int parm; /* PCSx Parameter*/
31 unsigned int stat1; /* PCSx Status 1 */
32 unsigned int stat2; /* PCSx Stusts 2 */
33 unsigned int pdd; /* PCSx PDD */
34};
35
36struct andes_pcu {
37 unsigned int rev; /* 0x00 - PCU Revision */
38 unsigned int spinfo; /* 0x04 - Scratch Pad Info */
39 unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */
40 unsigned int soc_id; /* 0x10 - SoC ID */
41 unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */
42 unsigned int soc_apb; /* 0x18 - SoC APB configuration */
43 unsigned int rsvd2; /* 0x1C */
44 unsigned int dcsrcr0; /* 0x20 - Driving Capability
45 and Slew Rate Control 0 */
46 unsigned int dcsrcr1; /* 0x24 - Driving Capability
47 and Slew Rate Control 1 */
48 unsigned int dcsrcr2; /* 0x28 - Driving Capability
49 and Slew Rate Control 2 */
50 unsigned int rsvd3; /* 0x2C */
51 unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */
52 unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */
53 unsigned int dmaes; /* 0x38 - DMA Engine Selection */
54 unsigned int rsvd4; /* 0x3C */
55 unsigned int oscc; /* 0x40 - OSC Control */
56 unsigned int pwmcd; /* 0x44 - PWM Clock divider */
57 unsigned int socmisc; /* 0x48 - SoC Misc. */
58 unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */
59 unsigned int bsmcr; /* 0x80 - BSM Controrl */
60 unsigned int bsmst; /* 0x84 - BSM Status */
61 unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/
62 unsigned int west; /* 0x8C - Wakeup Event Status */
63 unsigned int rsttiming; /* 0x90 - Reset Timing */
64 unsigned int intr_st; /* 0x94 - PCU Interrupt Status */
65 unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */
66 struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */
67 unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */
68 struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */
69 unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */
70 struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */
71 unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */
72 struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */
73 unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */
74 struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */
75 unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */
76 struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */
77 unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */
78 struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */
79 unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */
80 struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */
81 unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */
82 struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */
83 unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */
84 unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager
85 Scratch Pad Memory 0 */
86};
87#endif /* __ASSEMBLY__ */
88
89/*
90 * PCU Revision Register (ro)
91 */
92#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff)
93#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff)
94
95/*
96 * Scratch Pad Info Register (ro)
97 */
98#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff)
99#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf)
100
101/*
102 * SoC ID Register (ro)
103 */
104#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf)
105#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff)
106#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff)
107
108/*
109 * SoC AHB Configuration Register (ro)
110 */
111#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0)
112#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1)
113#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2)
114#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3)
115#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4)
116#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5)
117#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6)
118#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7)
119#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8)
120#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9)
121#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12)
122#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13)
123#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14)
124#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15)
125#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16)
126#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17)
127#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18)
128#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19)
129#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20)
130#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27)
131#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28)
132#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29)
133#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30)
134#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31)
135
136/*
137 * SoC APB Configuration Register (ro)
138 */
139#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1)
140#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2)
141#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3)
142#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5)
143#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6)
144#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8)
145#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16)
146#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17)
147#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18)
148#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19)
149#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20)
150#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22)
151#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23)
152
153/*
154 * Driving Capability and Slew Rate Control Register 0 (rw)
155 */
156#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0)
157#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8)
158#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12)
159#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16)
160#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20)
161
162/*
163 * Driving Capability and Slew Rate Control Register 1 (rw)
164 */
165#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0)
166
167/*
168 * Driving Capability and Slew Rate Control Register 2 (rw)
169 */
170#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0)
171#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4)
172#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8)
173#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12)
174#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16)
175#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20)
176#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24)
177#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28)
178
179/*
180 * Multi-function Port Setting Register 0 (rw)
181 */
182#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0)
183#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1)
184#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2)
185#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3)
186#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4)
187#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28)
188#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31)
189
190/*
191 * Multi-function Port Setting Register 1 (rw)
192 */
193#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0)
194#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1)
195#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2)
196#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3)
197#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4)
198#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5)
199#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6)
200#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7)
201#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8)
202#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9)
203#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10)
204#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27)
205#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28)
206#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29)
207#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30)
208#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31)
209
210/*
211 * DMA Engine Selection Register (rw)
212 */
213#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2)
214#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3)
215#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4)
216#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5)
217#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6)
218#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7)
219#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8)
220#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9)
221
222/*
223 * OSC Control Register (rw)
224 */
225#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0)
226#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1)
227#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2)
228#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4)
229#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6)
230#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8)
231
232/*
233 * PWM Clock Divider Register (rw)
234 */
235#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0)
236
237/*
238 * SoC Misc. Register (rw)
239 */
240#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0)
241#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1)
242#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2)
243#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3)
244#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4)
245#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6)
246#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8)
247#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9)
248#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10)
249#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11)
250#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12)
251#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13)
252#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14)
253#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15)
254#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16)
255#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17)
256#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18)
257#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19)
258#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20)
259#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21)
260#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22)
261#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23)
262#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24)
263#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25)
264#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26)
265#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27)
266#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28)
267#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29)
268#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30)
269#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31)
270
271/*
272 * BSM Control Register (rw)
273 */
274#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0)
275#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4)
276#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24)
277#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28)
278#define ANDES_PCU_BSMCR_IE(x) ((x) << 31)
279
280/*
281 * BSM Status Register
282 */
283#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0)
284#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4)
285#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24)
286#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28)
287
288/*
289 * Wakeup Event Sensitivity Register (rw)
290 */
291#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0)
292
293/*
294 * Wakeup Event Status Register (ro)
295 */
296#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0)
297
298/*
299 * Reset Timing Register
300 */
301#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0)
302#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8)
303#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16)
304#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24)
305
306/*
307 * PCU Interrupt Status Register
308 */
309#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0)
310#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1)
311#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2)
312#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3)
313#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4)
314#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5)
315#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6)
316#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7)
317#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8)
318#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9)
319
320/*
321 * PCSx Configuration Register
322 */
323#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0)
324#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16)
325#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20)
326#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */
327
328/*
329 * PCSx Parameter Register (rw)
330 */
331#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0)
332#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24)
333#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28)
334#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31)
335
336/*
337 * PCSx Status Register 1
338 */
339#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0)
340#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28)
341
342/*
343 * PCSx Status Register 2
344 */
345#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0)
346#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24)
347
348/*
349 * PCSx PDD Register
350 * This is reserved for PCS(1-7)
351 */
352#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0)
353#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8)
354#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16)
355#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24)
356
357#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0)
358#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6)
359#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12)
360#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18)
361#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24)
362#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27)
363#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28)
364#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30)
365#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31)
366
367#endif /* __ANDES_PCU_H */