blob: a5fd37f46b207c9c3e1d50f5dcd9dff087c8c89b [file] [log] [blame]
Bo Shen927b9012014-11-10 15:24:02 +08001/*
2 * Configuration settings for the SAMA5D4EK board.
3 *
4 * Copyright (C) 2014 Atmel
5 * Bo Shen <voice.shen@atmel.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Wu, Joshb2d387b2015-03-30 14:51:19 +080013#include "at91-sama5_common.h"
Bo Shen927b9012014-11-10 15:24:02 +080014
Bo Shen927b9012014-11-10 15:24:02 +080015/* SDRAM */
16#define CONFIG_NR_DRAM_BANKS 1
17#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
18#define CONFIG_SYS_SDRAM_SIZE 0x20000000
19
Bo Shen5a4c9c22014-12-15 13:24:38 +080020#ifdef CONFIG_SPL_BUILD
Wenyou Yangef33aa32017-04-13 10:31:19 +080021#define CONFIG_SYS_INIT_SP_ADDR 0x218000
Bo Shen5a4c9c22014-12-15 13:24:38 +080022#else
Bo Shen927b9012014-11-10 15:24:02 +080023#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yangef33aa32017-04-13 10:31:19 +080024 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shen5a4c9c22014-12-15 13:24:38 +080025#endif
Bo Shen927b9012014-11-10 15:24:02 +080026
27#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
28
Bo Shen927b9012014-11-10 15:24:02 +080029#ifdef CONFIG_CMD_SF
Bo Shen927b9012014-11-10 15:24:02 +080030#define CONFIG_SF_DEFAULT_SPEED 30000000
31#endif
32
33/* NAND flash */
34#define CONFIG_CMD_NAND
35
36#ifdef CONFIG_CMD_NAND
37#define CONFIG_NAND_ATMEL
38#define CONFIG_SYS_MAX_NAND_DEVICE 1
39#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
40/* our ALE is AD21 */
41#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
42/* our CLE is AD22 */
43#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
44#define CONFIG_SYS_NAND_ONFI_DETECTION
45/* PMECC & PMERRLOC */
46#define CONFIG_ATMEL_NAND_HWECC
47#define CONFIG_ATMEL_NAND_HW_PMECC
48#endif
49
Bo Shen927b9012014-11-10 15:24:02 +080050/* LCD */
Bo Shen927b9012014-11-10 15:24:02 +080051#define LCD_BPP LCD_COLOR16
52#define LCD_OUTPUT_BPP 18
53#define CONFIG_LCD_LOGO
54#define CONFIG_LCD_INFO
55#define CONFIG_LCD_INFO_BELOW_LOGO
56#define CONFIG_SYS_WHITE_ON_BLACK
57#define CONFIG_ATMEL_HLCD
58#define CONFIG_ATMEL_LCD_RGB565
Bo Shen927b9012014-11-10 15:24:02 +080059
60#ifdef CONFIG_SYS_USE_SERIALFLASH
Wu, Josh7a53b952015-08-19 19:11:21 +080061/* override the bootcmd, bootargs and other configuration for spi flash env*/
Bo Shen927b9012014-11-10 15:24:02 +080062#elif CONFIG_SYS_USE_NANDFLASH
Wu, Joshdc018fe2015-08-19 19:11:20 +080063/* override the bootcmd, bootargs and other configuration for nandflash env*/
Bo Shen927b9012014-11-10 15:24:02 +080064#elif CONFIG_SYS_USE_MMC
Wu, Josh372ca032015-08-19 19:11:18 +080065/* override the bootcmd, bootargs and other configuration for sd/mmc env */
Bo Shen927b9012014-11-10 15:24:02 +080066#endif
67
Bo Shen5a4c9c22014-12-15 13:24:38 +080068/* SPL */
69#define CONFIG_SPL_FRAMEWORK
70#define CONFIG_SPL_TEXT_BASE 0x200000
Wenyou Yangef33aa32017-04-13 10:31:19 +080071#define CONFIG_SPL_MAX_SIZE 0x18000
Bo Shen5a4c9c22014-12-15 13:24:38 +080072#define CONFIG_SPL_BSS_START_ADDR 0x20000000
73#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
74#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
75#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
76
Bo Shen5a4c9c22014-12-15 13:24:38 +080077#define CONFIG_SPL_BOARD_INIT
78#define CONFIG_SYS_MONITOR_LEN (512 << 10)
79
80#ifdef CONFIG_SYS_USE_MMC
Bo Shen993ea972015-03-04 13:32:57 +080081#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
Bo Shen5a4c9c22014-12-15 13:24:38 +080082#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
83#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shen5a4c9c22014-12-15 13:24:38 +080084
85#elif CONFIG_SYS_USE_NANDFLASH
Bo Shen5a4c9c22014-12-15 13:24:38 +080086#define CONFIG_SPL_NAND_DRIVERS
87#define CONFIG_SPL_NAND_BASE
88#define CONFIG_PMECC_CAP 8
89#define CONFIG_PMECC_SECTOR_SIZE 512
90#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
91#define CONFIG_SYS_NAND_5_ADDR_CYCLE
92#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
93#define CONFIG_SYS_NAND_PAGE_COUNT 64
94#define CONFIG_SYS_NAND_OOBSIZE 224
95#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
96#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
97#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
98
99#elif CONFIG_SYS_USE_SERIALFLASH
Bo Shen5a4c9c22014-12-15 13:24:38 +0800100#define CONFIG_SPL_SPI_LOAD
Wenyou Yangef33aa32017-04-13 10:31:19 +0800101#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
Bo Shen5a4c9c22014-12-15 13:24:38 +0800102
103#endif
Bo Shen927b9012014-11-10 15:24:02 +0800104#endif