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Stefan Roese13b4f632012-08-14 15:04:19 +02001/*
Stefan Roese8aa34492013-04-25 23:20:23 +00002 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
Stefan Roese13b4f632012-08-14 15:04:19 +02003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese13b4f632012-08-14 15:04:19 +02005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10/*
11 * High Level Configuration Options
12 * (easy to change)
13 */
14
15#define CONFIG_MPC5200
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090016#define CONFIG_A3M071 /* A3M071 board */
Stefan Roese13b4f632012-08-14 15:04:19 +020017
18#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
19
Stefan Roesed4451d32013-02-07 02:10:11 +000020#define CONFIG_SPL_TARGET "u-boot-img.bin"
21
Stefan Roese13b4f632012-08-14 15:04:19 +020022#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
23
24#define CONFIG_MISC_INIT_R
25#define CONFIG_SYS_LOWBOOT /* Enable lowboot */
26
Stefan Roesed4451d32013-02-07 02:10:11 +000027#ifdef CONFIG_A4M2K
28#define CONFIG_HOSTNAME a4m2k
29#else
30#define CONFIG_HOSTNAME a3m071
31#endif
32
Stefan Roesed62a89b2013-06-22 16:16:25 +020033#define CONFIG_BOOTCOUNT_LIMIT
34
Stefan Roese13b4f632012-08-14 15:04:19 +020035/*
36 * Serial console configuration
37 */
38#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
39#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
40#define CONFIG_SYS_BAUDRATE_TABLE \
41 { 9600, 19200, 38400, 57600, 115200, 230400 }
42
43/*
44 * Command line configuration.
45 */
46#include <config_cmd_default.h>
47
48#define CONFIG_CMD_BSP
49#define CONFIG_CMD_CACHE
Stefan Roese13b4f632012-08-14 15:04:19 +020050#define CONFIG_CMD_MII
51#define CONFIG_CMD_REGINFO
Stefan Roese8aa34492013-04-25 23:20:23 +000052#define CONFIG_CMD_DHCP
53#define CONFIG_BOOTP_SEND_HOSTNAME
54#define CONFIG_BOOTP_SERVERIP
55#define CONFIG_BOOTP_MAY_FAIL
56#define CONFIG_BOOTP_BOOTPATH
57#define CONFIG_BOOTP_GATEWAY
58#define CONFIG_BOOTP_SERVERIP
59#define CONFIG_NET_RETRY_COUNT 3
60#define CONFIG_CMD_LINK_LOCAL
Przemyslaw Marczak3c1c68c2014-03-25 10:58:19 +010061#define CONFIG_LIB_RAND
Stefan Roese8aa34492013-04-25 23:20:23 +000062#define CONFIG_NETCONSOLE
63#define CONFIG_SYS_CONSOLE_IS_IN_ENV
64#define CONFIG_CMD_PING
65#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
66#define CONFIG_MTD_PARTITIONS /* needed for UBI */
67#define CONFIG_FLASH_CFI_MTD
68#define MTDIDS_DEFAULT "nor0=fc000000.flash"
69#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
Stefan Roesed62a89b2013-06-22 16:16:25 +020070 "128k(env1)," \
71 "128k(env2)," \
Stefan Roese8aa34492013-04-25 23:20:23 +000072 "128k(hwinfo)," \
73 "1M(nvramsim)," \
74 "128k(dtb)," \
75 "5M(kernel)," \
76 "128k(sysinfo)," \
77 "7552k(root)," \
78 "4M(app)," \
Stefan Roesed62a89b2013-06-22 16:16:25 +020079 "5376k(data)," \
80 "8M(install)"
81
Stefan Roese8aa34492013-04-25 23:20:23 +000082#define CONFIG_LZO /* needed for UBI */
83#define CONFIG_RBTREE /* needed for UBI */
84#define CONFIG_CMD_MTDPARTS
85#define CONFIG_CMD_UBI
86#define CONFIG_CMD_UBIFS
87#define CONFIG_FIT
Stefan Roese13b4f632012-08-14 15:04:19 +020088
89/*
90 * IPB Bus clocking configuration.
91 */
92#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
93/* define for 66MHz speed - undef for 33MHz PCI clock speed */
Stefan Roesed4451d32013-02-07 02:10:11 +000094#ifdef CONFIG_A4M2K
95#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
96#else
Stefan Roese13b4f632012-08-14 15:04:19 +020097#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Stefan Roesed4451d32013-02-07 02:10:11 +000098#endif
Stefan Roese13b4f632012-08-14 15:04:19 +020099
100/* pass open firmware flat tree */
101#define CONFIG_OF_LIBFDT
102#define CONFIG_OF_BOARD_SETUP
103
104/* maximum size of the flat tree (8K) */
105#define OF_FLAT_TREE_MAX_SIZE 8192
106
107#define OF_CPU "PowerPC,5200@0"
108#define OF_SOC "soc5200@f0000000"
109#define OF_TBCLK (bd->bi_busfreq / 4)
110#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
111
112/*
Stefan Roese13b4f632012-08-14 15:04:19 +0200113 * NOR flash configuration
114 */
115#define CONFIG_SYS_FLASH_BASE 0xfc000000
Stefan Roesed4451d32013-02-07 02:10:11 +0000116#define CONFIG_SYS_FLASH_SIZE 0x02000000
Stefan Roese8aa34492013-04-25 23:20:23 +0000117#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
Stefan Roese13b4f632012-08-14 15:04:19 +0200118
119#define CONFIG_SYS_MAX_FLASH_BANKS 1
120#define CONFIG_SYS_MAX_FLASH_SECT 256
121#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
122#define CONFIG_SYS_FLASH_WRITE_TOUT 500
123#define CONFIG_SYS_FLASH_LOCK_TOUT 5
124#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
125#define CONFIG_SYS_FLASH_PROTECTION
126#define CONFIG_FLASH_CFI_DRIVER
127#define CONFIG_SYS_FLASH_CFI
128#define CONFIG_SYS_FLASH_EMPTY_INFO
129#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Stefan Roesef8945512013-04-04 03:55:42 +0000130#define CONFIG_FLASH_VERIFY
Stefan Roese13b4f632012-08-14 15:04:19 +0200131
132/*
133 * Environment settings
134 */
135#define CONFIG_ENV_IS_IN_FLASH
136#define CONFIG_ENV_SIZE 0x10000
137#define CONFIG_ENV_SECT_SIZE 0x20000
138#define CONFIG_ENV_OVERWRITE
Stefan Roese8aa34492013-04-25 23:20:23 +0000139#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
140#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese13b4f632012-08-14 15:04:19 +0200141
142/*
143 * Memory map
144 */
145#define CONFIG_SYS_MBAR 0xf0000000
146#define CONFIG_SYS_SDRAM_BASE 0x00000000
147#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
148
149/* Use SRAM until RAM will be available */
150#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
151#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
152
Stefan Roese13b4f632012-08-14 15:04:19 +0200153#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
Stefan Roese704afcc2013-04-25 23:10:02 +0000154 GENERATED_GBL_DATA_SIZE)
Stefan Roese13b4f632012-08-14 15:04:19 +0200155#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
156
157#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
158
Stefan Roese8aa34492013-04-25 23:20:23 +0000159#define CONFIG_SYS_MONITOR_LEN (512 << 10)
160#define CONFIG_SYS_MALLOC_LEN (4 << 20)
Stefan Roese13b4f632012-08-14 15:04:19 +0200161#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
162
163/*
164 * Ethernet configuration
165 */
166#define CONFIG_MPC5xxx_FEC
167#define CONFIG_MPC5xxx_FEC_MII100
Stefan Roesed4451d32013-02-07 02:10:11 +0000168#ifdef CONFIG_A4M2K
169#define CONFIG_PHY_ADDR 0x01
170#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200171#define CONFIG_PHY_ADDR 0x00
Stefan Roesed4451d32013-02-07 02:10:11 +0000172#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200173
174/*
175 * GPIO configuration
176 */
177
178/*
179 * GPIO-config depends on failsave-level
180 * failsave 0 means just MPX-config, no digiboard, no fpga
181 * 1 means digiboard ok
182 * 2 means fpga ok
183 */
184
Stefan Roesed4451d32013-02-07 02:10:11 +0000185#ifdef CONFIG_A4M2K
Stefan Roese8aa34492013-04-25 23:20:23 +0000186#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
Stefan Roesed4451d32013-02-07 02:10:11 +0000187#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200188/* for failsave-level 0 - full failsave */
189#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
190/* for failsave-level 1 - only digiboard ok */
Stefan Roese8aa34492013-04-25 23:20:23 +0000191#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
Stefan Roese13b4f632012-08-14 15:04:19 +0200192/* for failsave-level 2 - all ok */
Stefan Roese8aa34492013-04-25 23:20:23 +0000193#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
Stefan Roesed4451d32013-02-07 02:10:11 +0000194#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200195
Stefan Roeseaed75482013-02-07 02:10:28 +0000196#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
197#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
198#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
199#endif
200
Stefan Roese13b4f632012-08-14 15:04:19 +0200201/*
202 * Configuration matrix
Stefan Roese8aa34492013-04-25 23:20:23 +0000203 * MSB LSB
Stefan Roesed4451d32013-02-07 02:10:11 +0000204 * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
Stefan Roese8aa34492013-04-25 23:20:23 +0000205 * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
206 * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
Stefan Roese13b4f632012-08-14 15:04:19 +0200207 * || ||| || | ||| | | | |
208 * || ||| || | ||| | | | | bit rev name
209 * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
210 * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
211 * ||| || | ||| | | | | 2 29 ALTs
212 * +++-++--+---+++-+---+---+---+- 3 28 ALTs
213 * ++-++--+---+++-+---+---+---+- 4 27 CS7
214 * +-++--+---+++-+---+---+---+- 5 26 CS6
215 * || | ||| | | | | 6 25 ATA
216 * ++--+---+++-+---+---+---+- 7 24 ATA
217 * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
218 * | ||| | | | | 9 22 IRDA
219 * | ||| | | | | 10 21 IRDA
220 * +---+++-+---+---+---+- 11 20 IRDA
221 * ||| | | | | 12 19 Ether
222 * ||| | | | | 13 18 Ether
223 * ||| | | | | 14 17 Ether
224 * +++-+---+---+---+- 15 16 Ether
225 * ++-+---+---+---+- 16 15 PCI_DIS
226 * +-+---+---+---+- 17 14 USB_SE
227 * | | | | 18 13 USB
228 * +---+---+---+- 19 12 USB
229 * | | | 20 11 PSC3
230 * | | | 21 10 PSC3
231 * | | | 22 9 PSC3
232 * +---+---+- 23 8 PSC3
233 * | | 24 7 -
234 * | | 25 6 PSC2
235 * | | 26 5 PSC2
236 * +---+- 27 4 PSC2
237 * | 28 3 -
238 * | 29 2 PSC1
239 * | 30 1 PSC1
240 * +- 31 0 PSC1
241 */
242
243
244/*
245 * Miscellaneous configurable options
246 */
247#define CONFIG_SYS_LONGHELP
Stefan Roese13b4f632012-08-14 15:04:19 +0200248
249#define CONFIG_CMDLINE_EDITING
250#define CONFIG_SYS_HUSH_PARSER
251#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
252
253#if defined(CONFIG_CMD_KGDB)
254#define CONFIG_SYS_CBSIZE 1024
255#else
256#define CONFIG_SYS_CBSIZE 256
257#endif
258#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
259#define CONFIG_SYS_MAXARGS 16
260#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
261
262#define CONFIG_SYS_MEMTEST_START 0x00100000
263#define CONFIG_SYS_MEMTEST_END 0x00f00000
264
265#define CONFIG_SYS_LOAD_ADDR 0x00100000
266
Stefan Roese13b4f632012-08-14 15:04:19 +0200267#define CONFIG_LOOPW
268#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
269
270/*
271 * Various low-level settings
272 */
273#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
274#define CONFIG_SYS_HID0_FINAL HID0_ICE
275
276#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
277#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
278#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
279#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Stefan Roesed4451d32013-02-07 02:10:11 +0000280
281#ifdef CONFIG_A4M2K
282/* external MRAM */
283#define CONFIG_SYS_CS1_START 0xf1000000
284#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
285#endif
286
Stefan Roese13b4f632012-08-14 15:04:19 +0200287#define CONFIG_SYS_CS2_START 0xe0000000
288#define CONFIG_SYS_CS2_SIZE 0x00100000
289
Stefan Roesed4451d32013-02-07 02:10:11 +0000290/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
Stefan Roese13b4f632012-08-14 15:04:19 +0200291#define CONFIG_SYS_CS3_START 0xE9000000
Stefan Roesed4451d32013-02-07 02:10:11 +0000292#ifdef CONFIG_A4M2K
293#define CONFIG_SYS_CS3_SIZE 0x00100000
294#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200295#define CONFIG_SYS_CS3_SIZE 0x00080000
Stefan Roesed4451d32013-02-07 02:10:11 +0000296#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200297/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
298#define CONFIG_SYS_CS3_CFG 0x0032B900
299
Stefan Roesed4451d32013-02-07 02:10:11 +0000300#ifndef CONFIG_A4M2K
Stefan Roese13b4f632012-08-14 15:04:19 +0200301/* Diagnosis Interface - see ticket #63 */
302#define CONFIG_SYS_CS4_START 0xEA000000
303#define CONFIG_SYS_CS4_SIZE 0x00000001
304/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
305#define CONFIG_SYS_CS4_CFG 0x0002B900
Stefan Roesed4451d32013-02-07 02:10:11 +0000306#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200307
Stefan Roesed4451d32013-02-07 02:10:11 +0000308/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
Stefan Roese13b4f632012-08-14 15:04:19 +0200309#define CONFIG_SYS_CS5_START 0xE8000000
Stefan Roesed4451d32013-02-07 02:10:11 +0000310#ifdef CONFIG_A4M2K
311#define CONFIG_SYS_CS5_SIZE 0x00100000
312#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200313#define CONFIG_SYS_CS5_SIZE 0x00010000
Stefan Roesed4451d32013-02-07 02:10:11 +0000314#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200315/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
316#define CONFIG_SYS_CS5_CFG 0x0032B900
317
318#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
319#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
Stefan Roesed4451d32013-02-07 02:10:11 +0000320#define CONFIG_SYS_CS1_CFG 0x0008FD00
Stefan Roese13b4f632012-08-14 15:04:19 +0200321#define CONFIG_SYS_CS2_CFG 0x0006F90C
322#else /* for pci_clk = 33 MHz */
323#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
324#define CONFIG_SYS_CS1_CFG 0x0001FB00
325#define CONFIG_SYS_CS2_CFG 0x0002F90C
326#endif
327
328#define CONFIG_SYS_CS_BURST 0x00000000
329/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
330/* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
331/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
332#define CONFIG_SYS_CS_DEADCYCLE 0x33030000
333
334#define CONFIG_SYS_RESET_ADDRESS 0xff000000
335
336/*
337 * Environment Configuration
338 */
339
Stefan Roese8aa34492013-04-25 23:20:23 +0000340#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
Stefan Roese13b4f632012-08-14 15:04:19 +0200341#undef CONFIG_BOOTARGS
342#define CONFIG_ZERO_BOOTDELAY_CHECK
343
Stefan Roese8aa34492013-04-25 23:20:23 +0000344#define CONFIG_SYS_AUTOLOAD "n"
345
Stefan Roese13b4f632012-08-14 15:04:19 +0200346#define CONFIG_PREBOOT "echo;" \
347 "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
348 "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
349 "echo"
350
351#undef CONFIG_BOOTARGS
352
Stefan Roese8aa34492013-04-25 23:20:23 +0000353#define CONFIG_SYS_OS_BASE 0xfc200000
354#define CONFIG_SYS_FDT_BASE 0xfc1e0000
Stefan Roese13b4f632012-08-14 15:04:19 +0200355
Stefan Roese13b4f632012-08-14 15:04:19 +0200356#define CONFIG_EXTRA_ENV_SETTINGS \
357 "netdev=eth0\0" \
358 "verify=no\0" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000359 "loadaddr=200000\0" \
360 "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
361 "kernel_addr_r=1000000\0" \
362 "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
363 "fdt_addr_r=1800000\0" \
364 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
365 "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
366 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
367 "rootpath=/opt/eldk-5.2.1/powerpc/" \
368 "core-image-minimal-mtdutils-dropbear-generic\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200369 "consoledev=ttyPSC0\0" \
370 "nfsargs=setenv bootargs root=/dev/nfs rw " \
371 "nfsroot=${serverip}:${rootpath}\0" \
372 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200373 "mtdargs=setenv bootargs root=/dev/mtdblock8 " \
Stefan Roese8aa34492013-04-25 23:20:23 +0000374 "rootfstype=squashfs,jffs2\0" \
375 "addhost=setenv bootargs ${bootargs} " \
376 "hostname=${hostname}\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200377 "addip=setenv bootargs ${bootargs} " \
378 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
379 ":${hostname}:${netdev}:off panic=1\0" \
380 "addtty=setenv bootargs ${bootargs} " \
381 "console=${consoledev},${baudrate}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200382 "flash_nfs=run nfsargs addip addtty addmtd addhost;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000383 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200384 "flash_mtd=run mtdargs addip addtty addmtd addhost;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000385 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200386 "flash_self=run ramargs addip addtty addmtd addhost;" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000387 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
388 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
389 "tftp ${fdt_addr_r} ${fdtfile};" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200390 "run nfsargs addip addtty addmtd addhost;" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000391 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
392 "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
393 "/u-boot-img.bin\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200394 "update=protect off fc000000 fc07ffff;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000395 "era fc000000 fc07ffff;" \
396 "cp.b ${loadaddr} fc000000 ${filesize}\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200397 "upd=run load;run update\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200398 "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
399 "run mtdargs addip addtty addmtd addhost;" \
400 "fdt addr 1800000;fdt boardsetup;fdt chosen;" \
401 "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
402 "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
403 "erase fc200000 fc6fffff;" \
404 "cp.b 1000000 fc200000 ${filesize}" \
405 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
406 "mtdids=" MTDIDS_DEFAULT "\0" \
407 "mtdparts=" MTDPARTS_DEFAULT "\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200408 ""
409
410#define CONFIG_BOOTCOMMAND "run flash_mtd"
411
412/*
413 * SPL related defines
414 */
415#define CONFIG_SPL
416#define CONFIG_SPL_FRAMEWORK
Stefan Roesed4451d32013-02-07 02:10:11 +0000417#define CONFIG_SPL_BOARD_INIT
Stefan Roese13b4f632012-08-14 15:04:19 +0200418#define CONFIG_SPL_NOR_SUPPORT
419#define CONFIG_SPL_TEXT_BASE 0xfc000000
420#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
421#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
422#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
423#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
424#define CONFIG_SPL_SERIAL_SUPPORT
425
426/* Place BSS for SPL near end of SDRAM */
427#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
428#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
429
430#define CONFIG_SPL_OS_BOOT
Ying Zhangba1bee42013-05-20 14:07:25 +0800431#define CONFIG_SPL_ENV_SUPPORT
Stefan Roese13b4f632012-08-14 15:04:19 +0200432/* Place patched DT blob (fdt) at this address */
433#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
434
435/* Settings for real U-Boot to be loaded from NOR flash */
436#ifndef __ASSEMBLY__
437extern char __spl_flash_end[];
438#endif
439#define CONFIG_SYS_UBOOT_BASE __spl_flash_end
440#define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
441#define CONFIG_SYS_UBOOT_START 0x1000100
442
443#endif /* __CONFIG_H */