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Vipin KUMAR5b1b1882010-06-29 10:53:34 +05301/*
2 * (C) Copyright 2010
3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05306 */
7
8#ifndef _DW_ETH_H
9#define _DW_ETH_H
10
11#define CONFIG_TX_DESCR_NUM 16
12#define CONFIG_RX_DESCR_NUM 16
13#define CONFIG_ETH_BUFSIZE 2048
14#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
15#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
16
17#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
18#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053019
20struct eth_mac_regs {
21 u32 conf; /* 0x00 */
22 u32 framefilt; /* 0x04 */
23 u32 hashtablehigh; /* 0x08 */
24 u32 hashtablelow; /* 0x0c */
25 u32 miiaddr; /* 0x10 */
26 u32 miidata; /* 0x14 */
27 u32 flowcontrol; /* 0x18 */
28 u32 vlantag; /* 0x1c */
29 u32 version; /* 0x20 */
30 u8 reserved_1[20];
31 u32 intreg; /* 0x38 */
32 u32 intmask; /* 0x3c */
33 u32 macaddr0hi; /* 0x40 */
34 u32 macaddr0lo; /* 0x44 */
35};
36
37/* MAC configuration register definitions */
38#define FRAMEBURSTENABLE (1 << 21)
39#define MII_PORTSELECT (1 << 15)
40#define FES_100 (1 << 14)
41#define DISABLERXOWN (1 << 13)
42#define FULLDPLXMODE (1 << 11)
43#define RXENABLE (1 << 2)
44#define TXENABLE (1 << 3)
45
46/* MII address register definitions */
47#define MII_BUSY (1 << 0)
48#define MII_WRITE (1 << 1)
49#define MII_CLKRANGE_60_100M (0)
50#define MII_CLKRANGE_100_150M (0x4)
51#define MII_CLKRANGE_20_35M (0x8)
52#define MII_CLKRANGE_35_60M (0xC)
53#define MII_CLKRANGE_150_250M (0x10)
54#define MII_CLKRANGE_250_300M (0x14)
55
56#define MIIADDRSHIFT (11)
57#define MIIREGSHIFT (6)
58#define MII_REGMSK (0x1F << 6)
59#define MII_ADDRMSK (0x1F << 11)
60
61
62struct eth_dma_regs {
63 u32 busmode; /* 0x00 */
64 u32 txpolldemand; /* 0x04 */
65 u32 rxpolldemand; /* 0x08 */
66 u32 rxdesclistaddr; /* 0x0c */
67 u32 txdesclistaddr; /* 0x10 */
68 u32 status; /* 0x14 */
69 u32 opmode; /* 0x18 */
70 u32 intenable; /* 0x1c */
Sonic Zhang2ddaf132015-01-29 13:37:31 +080071 u32 reserved1[2];
72 u32 axibus; /* 0x28 */
73 u32 reserved2[7];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053074 u32 currhosttxdesc; /* 0x48 */
75 u32 currhostrxdesc; /* 0x4c */
76 u32 currhosttxbuffaddr; /* 0x50 */
77 u32 currhostrxbuffaddr; /* 0x54 */
78};
79
80#define DW_DMA_BASE_OFFSET (0x1000)
81
Ian Campbell49692c52014-05-08 22:26:35 +010082/* Default DMA Burst length */
83#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
84#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
85#endif
86
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053087/* Bus mode register definitions */
88#define FIXEDBURST (1 << 16)
89#define PRIORXTX_41 (3 << 14)
90#define PRIORXTX_31 (2 << 14)
91#define PRIORXTX_21 (1 << 14)
92#define PRIORXTX_11 (0 << 14)
Ian Campbell49692c52014-05-08 22:26:35 +010093#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053094#define RXHIGHPRIO (1 << 1)
95#define DMAMAC_SRST (1 << 0)
96
97/* Poll demand definitions */
98#define POLL_DATA (0xFFFFFFFF)
99
100/* Operation mode definitions */
101#define STOREFORWARD (1 << 21)
102#define FLUSHTXFIFO (1 << 20)
103#define TXSTART (1 << 13)
104#define TXSECONDFRAME (1 << 2)
105#define RXSTART (1 << 1)
106
107/* Descriptior related definitions */
Vipin KUMAR97a6caa2012-03-26 00:09:53 +0000108#define MAC_MAX_FRAME_SZ (1600)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530109
110struct dmamacdescr {
111 u32 txrx_status;
112 u32 dmamac_cntl;
113 void *dmamac_addr;
114 struct dmamacdescr *dmamac_next;
Alexey Brodkina7b26db2014-03-21 16:16:57 +0400115} __aligned(ARCH_DMA_MINALIGN);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530116
117/*
118 * txrx_status definitions
119 */
120
121/* tx status bits definitions */
122#if defined(CONFIG_DW_ALTDESCRIPTOR)
123
124#define DESC_TXSTS_OWNBYDMA (1 << 31)
125#define DESC_TXSTS_TXINT (1 << 30)
126#define DESC_TXSTS_TXLAST (1 << 29)
127#define DESC_TXSTS_TXFIRST (1 << 28)
128#define DESC_TXSTS_TXCRCDIS (1 << 27)
129
130#define DESC_TXSTS_TXPADDIS (1 << 26)
131#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
132#define DESC_TXSTS_TXRINGEND (1 << 21)
133#define DESC_TXSTS_TXCHAIN (1 << 20)
134#define DESC_TXSTS_MSK (0x1FFFF << 0)
135
136#else
137
138#define DESC_TXSTS_OWNBYDMA (1 << 31)
139#define DESC_TXSTS_MSK (0x1FFFF << 0)
140
141#endif
142
143/* rx status bits definitions */
144#define DESC_RXSTS_OWNBYDMA (1 << 31)
145#define DESC_RXSTS_DAFILTERFAIL (1 << 30)
146#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
147#define DESC_RXSTS_FRMLENSHFT (16)
148
149#define DESC_RXSTS_ERROR (1 << 15)
150#define DESC_RXSTS_RXTRUNCATED (1 << 14)
151#define DESC_RXSTS_SAFILTERFAIL (1 << 13)
152#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
153#define DESC_RXSTS_RXDAMAGED (1 << 11)
154#define DESC_RXSTS_RXVLANTAG (1 << 10)
155#define DESC_RXSTS_RXFIRST (1 << 9)
156#define DESC_RXSTS_RXLAST (1 << 8)
157#define DESC_RXSTS_RXIPC_GIANT (1 << 7)
158#define DESC_RXSTS_RXCOLLISION (1 << 6)
159#define DESC_RXSTS_RXFRAMEETHER (1 << 5)
160#define DESC_RXSTS_RXWATCHDOG (1 << 4)
161#define DESC_RXSTS_RXMIIERROR (1 << 3)
162#define DESC_RXSTS_RXDRIBBLING (1 << 2)
163#define DESC_RXSTS_RXCRC (1 << 1)
164
165/*
166 * dmamac_cntl definitions
167 */
168
169/* tx control bits definitions */
170#if defined(CONFIG_DW_ALTDESCRIPTOR)
171
172#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
173#define DESC_TXCTRL_SIZE1SHFT (0)
174#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
175#define DESC_TXCTRL_SIZE2SHFT (16)
176
177#else
178
179#define DESC_TXCTRL_TXINT (1 << 31)
180#define DESC_TXCTRL_TXLAST (1 << 30)
181#define DESC_TXCTRL_TXFIRST (1 << 29)
182#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
183#define DESC_TXCTRL_TXCRCDIS (1 << 26)
184#define DESC_TXCTRL_TXRINGEND (1 << 25)
185#define DESC_TXCTRL_TXCHAIN (1 << 24)
186
187#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
188#define DESC_TXCTRL_SIZE1SHFT (0)
189#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
190#define DESC_TXCTRL_SIZE2SHFT (11)
191
192#endif
193
194/* rx control bits definitions */
195#if defined(CONFIG_DW_ALTDESCRIPTOR)
196
197#define DESC_RXCTRL_RXINTDIS (1 << 31)
198#define DESC_RXCTRL_RXRINGEND (1 << 15)
199#define DESC_RXCTRL_RXCHAIN (1 << 14)
200
201#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
202#define DESC_RXCTRL_SIZE1SHFT (0)
203#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
204#define DESC_RXCTRL_SIZE2SHFT (16)
205
206#else
207
208#define DESC_RXCTRL_RXINTDIS (1 << 31)
209#define DESC_RXCTRL_RXRINGEND (1 << 25)
210#define DESC_RXCTRL_RXCHAIN (1 << 24)
211
212#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
213#define DESC_RXCTRL_SIZE1SHFT (0)
214#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
215#define DESC_RXCTRL_SIZE2SHFT (11)
216
217#endif
218
219struct dw_eth_dev {
Ian Campbell18570752014-05-14 19:30:29 +0100220 struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
221 struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
222 char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
223 char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
224
Vipin Kumar9afc1af2012-05-07 13:06:44 +0530225 u32 interface;
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300226 u32 max_speed;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530227 u32 tx_currdescnum;
228 u32 rx_currdescnum;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530229
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530230 struct eth_mac_regs *mac_regs_p;
231 struct eth_dma_regs *dma_regs_p;
Simon Glass75577ba2015-04-05 16:07:41 -0600232#ifndef CONFIG_DM_ETH
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530233 struct eth_device *dev;
Simon Glass75577ba2015-04-05 16:07:41 -0600234#endif
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400235 struct phy_device *phydev;
236 struct mii_dev *bus;
Alexey Brodkined102be2013-09-25 19:27:48 +0400237};
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530238
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530239#endif