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Stefan Roese211ea912007-10-22 07:34:34 +02001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ppc4xx.h>
26#include <ppc405.h>
27#include <libfdt.h>
28#include <asm/processor.h>
Stefan Roeseecdcbd42007-11-16 14:00:59 +010029#include <asm/gpio.h>
30#include <asm/io.h>
Wolfgang Denk6eb3fb12008-01-13 16:07:44 +010031#include <fdt_support.h>
Stefan Roese211ea912007-10-22 07:34:34 +020032
33#if defined(CONFIG_PCI)
34#include <pci.h>
35#include <asm/4xx_pcie.h>
36#endif
37
38DECLARE_GLOBAL_DATA_PTR;
39
40extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
41
42/*
43 * Board early initialization function
44 */
45int board_early_init_f (void)
46{
Stefan Roese7cfc12a2007-12-08 14:47:34 +010047 u32 val;
48
Stefan Roese211ea912007-10-22 07:34:34 +020049 /*--------------------------------------------------------------------+
50 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
51 +--------------------------------------------------------------------+
52 +---------------------------------------------------------------------+
53 |Interrupt| Source | Pol. | Sensi.| Crit. |
54 +---------+-----------------------------------+-------+-------+-------+
55 | IRQ 00 | UART0 | High | Level | Non |
56 | IRQ 01 | UART1 | High | Level | Non |
57 | IRQ 02 | IIC0 | High | Level | Non |
58 | IRQ 03 | TBD | High | Level | Non |
59 | IRQ 04 | TBD | High | Level | Non |
60 | IRQ 05 | EBM | High | Level | Non |
61 | IRQ 06 | BGI | High | Level | Non |
62 | IRQ 07 | IIC1 | Rising| Edge | Non |
63 | IRQ 08 | SPI | High | Lvl/ed| Non |
64 | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
65 | IRQ 10 | MAL TX EOB | High | Level | Non |
66 | IRQ 11 | MAL RX EOB | High | Level | Non |
67 | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
68 | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
69 | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
70 | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
71 | IRQ 16 | PCIE0 AL | high | Level | Non |
72 | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
73 | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
74 | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
75 | IRQ 20 | PCIE0 TCR | High | Level | Non |
76 | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
77 | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
78 | IRQ 23 | Security EIP-94 | High | Level | Non |
79 | IRQ 24 | EMAC0 interrupt | High | Level | Non |
80 | IRQ 25 | EMAC1 interrupt | High | Level | Non |
81 | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
82 | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
83 | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
84 | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
85 | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
86 | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
87 |----------------------------------------------------------------------
88 | IRQ 32 | MAL Serr | High | Level | Non |
89 | IRQ 33 | MAL Txde | High | Level | Non |
90 | IRQ 34 | MAL Rxde | High | Level | Non |
91 | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
92 | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
93 | IRQ 37 | EBC | High |Lvl Edg| Non |
94 | IRQ 38 | NDFC | High | Level | Non |
95 | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
96 | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
97 | IRQ 41 | PCIE1 AL | high | Level | Non |
98 | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
99 | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
100 | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
101 | IRQ 45 | PCIE1 TCR | High | Level | Non |
102 | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
103 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
104 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
105 | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
106 | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
107 | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
108 | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
109 | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
110 | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
111 | IRQ 55 | Serial ROM | High | Level | Non |
112 | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
113 | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
114 | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
115 | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
116 | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
117 | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
118 | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
119 |----------------------------------------------------------------------
120 | IRQ 64 | PE0 AL | High | Level | Non |
121 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
122 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
123 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
124 | IRQ 68 | PE0 TCR | High | Level | Non |
125 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
126 | IRQ 70 | PE0 DCR Error | High | Level | Non |
127 | IRQ 71 | Reserved | N/A | N/A | Non |
128 | IRQ 72 | PE1 AL | High | Level | Non |
129 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
130 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
131 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
132 | IRQ 76 | PE1 TCR | High | Level | Non |
133 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
134 | IRQ 78 | PE1 DCR Error | High | Level | Non |
135 | IRQ 79 | Reserved | N/A | N/A | Non |
136 | IRQ 80 | PE2 AL | High | Level | Non |
137 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
138 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
139 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
140 | IRQ 84 | PE2 TCR | High | Level | Non |
141 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
142 | IRQ 86 | PE2 DCR Error | High | Level | Non |
143 | IRQ 87 | Reserved | N/A | N/A | Non |
144 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
145 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
146 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
147 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
148 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
149 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
150 | IRQ 94 | Reserved | N/A | N/A | Non |
151 | IRQ 95 | Reserved | N/A | N/A | Non |
152 |---------------------------------------------------------------------
153 +---------+-----------------------------------+-------+-------+------*/
154 /*--------------------------------------------------------------------+
155 | Initialise UIC registers. Clear all interrupts. Disable all
156 | interrupts.
157 | Set critical interrupt values. Set interrupt polarities. Set
158 | interrupt trigger levels. Make bit 0 High priority. Clear all
159 | interrupts again.
160 +-------------------------------------------------------------------*/
161
162 mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
163 mtdcr (uic2er, 0x00000000); /* disable all interrupts */
164 mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
165 mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
166 mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
167 mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
168 mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
169 mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
170
171 mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
172 mtdcr (uic1er, 0x00000000); /* disable all interrupts */
173 mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
174 mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
175 mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
176 mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
177 mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
178 mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
179
180 mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
181 mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
182 /* Except cascade UIC0 and UIC1 */
183 mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
184 mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
185 mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
186 mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
187 mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
188 mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
189
190 /*
191 * Note: Some cores are still in reset when the chip starts, so
192 * take them out of reset
193 */
194 mtsdr(SDR0_SRST, 0);
195
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100196 /* Reset PCIe slots */
197 gpio_write_bit(CFG_GPIO_PCIE_RST, 0);
198 udelay(100);
199 gpio_write_bit(CFG_GPIO_PCIE_RST, 1);
200
Stefan Roese7cfc12a2007-12-08 14:47:34 +0100201 /*
202 * Configure PFC (Pin Function Control) registers
203 * -> Enable USB
204 */
205 val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
206 mtsdr(SDR0_PFC1, val);
207
Stefan Roese211ea912007-10-22 07:34:34 +0200208 return 0;
209}
210
211int misc_init_r(void)
212{
213#ifdef CFG_ENV_IS_IN_FLASH
214 /* Monitor protection ON by default */
215 flash_protect(FLAG_PROTECT_SET,
216 -CFG_MONITOR_LEN,
217 0xffffffff,
218 &flash_info[0]);
219#endif
220
221 return 0;
222}
223
224int checkboard (void)
225{
226 char *s = getenv("serial#");
227
228 printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
229
230 if (s != NULL) {
231 puts(", serial# ");
232 puts(s);
233 }
234 putc('\n');
235
236 return (0);
237}
238
239/*************************************************************************
240 * pci_pre_init
241 *
242 * This routine is called just prior to registering the hose and gives
243 * the board the opportunity to check things. Returning a value of zero
244 * indicates that things are bad & PCI initialization should be aborted.
245 *
246 * Different boards may wish to customize the pci controller structure
247 * (add regions, override default access routines, etc) or perform
248 * certain pre-initialization actions.
249 *
250 ************************************************************************/
251#if defined(CONFIG_PCI)
252int pci_pre_init(struct pci_controller * hose )
253{
254 return 0;
255}
256#endif /* defined(CONFIG_PCI) */
257
Stefan Roese211ea912007-10-22 07:34:34 +0200258#ifdef CONFIG_PCI
259static struct pci_controller pcie_hose[2] = {{0},{0}};
260
261void pcie_setup_hoses(int busno)
262{
263 struct pci_controller *hose;
264 int i, bus;
265 int ret = 0;
266 bus = busno;
267 char *env;
268 unsigned int delay;
269
270 for (i = 0; i < 2; i++) {
271
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100272 if (is_end_point(i))
Stefan Roese211ea912007-10-22 07:34:34 +0200273 ret = ppc4xx_init_pcie_endport(i);
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100274 else
Stefan Roese211ea912007-10-22 07:34:34 +0200275 ret = ppc4xx_init_pcie_rootport(i);
Stefan Roese211ea912007-10-22 07:34:34 +0200276 if (ret) {
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100277 printf("PCIE%d: initialization as %s failed\n", i,
278 is_end_point(i) ? "endpoint" : "root-complex");
Stefan Roese211ea912007-10-22 07:34:34 +0200279 continue;
280 }
281
282 hose = &pcie_hose[i];
283 hose->first_busno = bus;
284 hose->last_busno = bus;
285 hose->current_busno = bus;
286
287 /* setup mem resource */
288 pci_set_region(hose->regions + 0,
289 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
290 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
291 CFG_PCIE_MEMSIZE,
292 PCI_REGION_MEM);
293 hose->region_count = 1;
294 pci_register_hose(hose);
295
296 if (is_end_point(i)) {
297 ppc4xx_setup_pcie_endpoint(hose, i);
298 /*
299 * Reson for no scanning is endpoint can not generate
300 * upstream configuration accesses.
301 */
302 } else {
303 ppc4xx_setup_pcie_rootpoint(hose, i);
304 env = getenv ("pciscandelay");
305 if (env != NULL) {
306 delay = simple_strtoul(env, NULL, 10);
307 if (delay > 5)
308 printf("Warning, expect noticable delay before "
309 "PCIe scan due to 'pciscandelay' value!\n");
310 mdelay(delay * 1000);
311 }
312
313 /*
314 * Config access can only go down stream
315 */
316 hose->last_busno = pci_hose_scan(hose);
317 bus = hose->last_busno + 1;
318 }
319 }
320}
321#endif
322
323#if defined(CONFIG_POST)
324/*
325 * Returns 1 if keys pressed to start the power-on long-running tests
326 * Called from board_init_f().
327 */
328int post_hotkeys_pressed(void)
329{
330 return 0; /* No hotkeys supported */
331}
332#endif /* CONFIG_POST */
333
334#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
335void ft_board_setup(void *blob, bd_t *bd)
336{
337 u32 val[4];
338 int rc;
339
340 ft_cpu_setup(blob, bd);
341
342 /* Fixup NOR mapping */
343 val[0] = 0; /* chip select number */
344 val[1] = 0; /* always 0 */
345 val[2] = gd->bd->bi_flashstart;
346 val[3] = gd->bd->bi_flashsize;
347 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
348 val, sizeof(val), 1);
349 if (rc)
350 printf("Unable to update property NOR mapping, err=%s\n",
351 fdt_strerror(rc));
352}
353#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */