blob: aeb04b96b4b6fcbf9838407e130636908dd1eabb [file] [log] [blame]
Simon Glass3a1a18f2015-01-27 22:13:47 -07001/*
2 * Copyright (C) 2015 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * board/config.h - configuration options, board specific
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#include <configs/x86-common.h>
15
16#define CONFIG_SYS_MONITOR_LEN (1 << 20)
Gabriel Huau5d3c2c52015-05-11 23:18:25 -070017#define CONFIG_ARCH_EARLY_INIT_R
Simon Glassef910812015-08-13 10:36:16 -060018#define CONFIG_ARCH_MISC_INIT
Simon Glass3a1a18f2015-01-27 22:13:47 -070019
Simon Glassdcfe4a52015-07-27 15:47:23 -060020#define CONFIG_SMSC_LPC47M
Simon Glass3a1a18f2015-01-27 22:13:47 -070021
Simon Glassb71f9dc2015-07-03 18:28:26 -060022#define CONFIG_PCI_CONFIG_HOST_BRIDGE
Simon Glass3a1a18f2015-01-27 22:13:47 -070023#define CONFIG_SYS_EARLY_PCI_INIT
24#define CONFIG_PCI_PNP
25#define CONFIG_RTL8169
26#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
27 "stdout=vga,serial\0" \
28 "stderr=vga,serial\0"
29
Bin Meng44a8b962015-08-06 02:36:01 -070030#define CONFIG_SCSI_DEV_LIST \
31 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
32 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
33
Gabriel Huau8ddb8cf2015-04-25 08:13:11 -070034#define CONFIG_SPI_FLASH_STMICRO
Simon Glass3a1a18f2015-01-27 22:13:47 -070035
36#define CONFIG_MMC
37#define CONFIG_SDHCI
38#define CONFIG_GENERIC_MMC
39#define CONFIG_MMC_SDMA
40#define CONFIG_CMD_MMC
41
42#undef CONFIG_USB_MAX_CONTROLLER_COUNT
43#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
44
Simon Glass3a1a18f2015-01-27 22:13:47 -070045#define VIDEO_IO_OFFSET 0
46#define CONFIG_X86EMU_RAW_IO
47#define CONFIG_VGA_AS_SINGLE_DEVICE
48
49#define CONFIG_FIT_SIGNATURE
50#define CONFIG_RSA
51
Simon Glassd5359f22015-07-03 18:28:23 -060052#define CONFIG_ENV_SECT_SIZE 0x1000
53#define CONFIG_ENV_OFFSET 0x007fe000
Bin Mengd21d05f2015-03-31 11:51:04 +080054
Simon Glass3a1a18f2015-01-27 22:13:47 -070055#endif /* __CONFIG_H */