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wdenk2d1a5372004-02-23 19:30:57 +00001/*
2 * Memory Setup stuff - taken from Linux
3 *
4 * Copyright (c) 2002 Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
5 * (c) 2004 IMMS gGmbH <www.imms.de>, Thomas Elste <info@elste.org>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26
27#include <config.h>
28#include <version.h>
29#include <asm/arch/netarm_registers.h>
30
31
32/* some parameters for the board */
33#define FLASH_90ns_WAIT_STATES ((NETARM_PLL_COUNT_VAL + 2) / 3)
34#define FLASH_70ns_WAIT_STATES 4
35
36#define NETARM_MMAP_CS0_BASE (PHYS_FLASH_1)
37#if 1
38#define NETARM_MMAP_CS0_MASK (~(PHYS_FLASH_1_SIZE - 1))
39#else
40#define NETARM_MMAP_CS0_MASK (~(1000000 - 1))
41#endif
42#define NETARM_MMAP_CS1_BASE (PHYS_SDRAM_1)
43#define NETARM_MMAP_CS1_MASK (~(PHYS_SDRAM_1_SIZE - 1))
44#define NETARM_MMAP_CS2_BASE (PHYS_SDRAM_2)
45#define NETARM_MMAP_CS2_MASK (~(PHYS_SDRAM_2_SIZE - 1))
46#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
47#define NETARM_MMAP_CS3_BASE (PHYS_NVRAM_1)
48#define NETARM_MMAP_CS3_MASK (~(PHYS_NVRAM_SIZE - 1))
49#endif
50#define NETARM_MMAP_CS4_BASE (PHYS_EXT_1)
51#define NETARM_MMAP_CS4_MASK (~(PHYS_EXT_SIZE - 1))
52
53/* setting up the memory */
54.globl memsetup
55memsetup:
56
57#if defined(CONFIG_MODNET50)
58 ldr pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - TEXT_BASE)
59
60_jump_to_high:
61 /*
62 * MEM Config Reg
63 * ---------------------------------------------------
64 */
65 ldr r0, =NETARM_MEM_MODULE_BASE
66 ldr r1, =( NETARM_MEM_REFR_PERIOD_USEC(16) | \
67 NETARM_MEM_CFG_REFRESH_EN | \
68 NETARM_MEM_CFG_REFR_CYCLE_5CLKS )
69 str r1, [r0, #+NETARM_MEM_MODULE_CONFIG]
70
71
72memsetup_cs0:
73 /*
74 * Base Addr / Option Reg 0 (Flash)
75 * ---------------------------------------------------
76 */
77 ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS0_BASE) | \
78 NETARM_MEM_BAR_DRAM_FP | \
79 NETARM_MEM_BAR_DRAM_MUX_INT | \
80 NETARM_MEM_BAR_DRAM_MUX_BAL | \
81 NETARM_MEM_BAR_VALID )
82 str r1, [r0, #+NETARM_MEM_CS0_BASE_ADDR]
83
84 /* trust that the bus size for flash was strapped correctly */
85 /* this saves the bus width in r2 and then ORs it back in */
86 /* it's pretty safe assumption, otherwise it wouldn't boot */
87 ldr r2, [r0, #+NETARM_MEM_CS0_OPTIONS]
88 and r2, r2, #NETARM_MEM_OPT_BUS_SIZE_MASK
89
90/* just a test: assume 32 bit flash mem */
91/* mov r2, #NETARM_MEM_OPT_32BIT */
92
93 ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS0_MASK) | \
94 NETARM_MEM_OPT_WAIT_STATES(FLASH_70ns_WAIT_STATES) | \
95 NETARM_MEM_OPT_BCYC_4 | \
96 NETARM_MEM_OPT_BSIZE_16 | \
97 NETARM_MEM_OPT_16BIT | \
98 NETARM_MEM_OPT_READ_ASYNC | \
99 NETARM_MEM_OPT_WRITE_ASYNC )
100
101 orr r1, r1, r2
102 str r1, [r0, #+NETARM_MEM_CS0_OPTIONS]
103
104
105memsetup_cs1:
106 /*
107 * Base Addr / Option Reg 1 (DRAM #1)
108 * ---------------------------------------------------
109 */
110#ifdef CONFIG_NETARM_NET40_REV2
111 /* we have to config SDRAM in burst mode */
112 ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
113 NETARM_MEM_OPT_BCYC_2 | \
114 NETARM_MEM_OPT_BSIZE_16 | \
115 NETARM_MEM_OPT_WAIT_STATES(0) | \
116 NETARM_MEM_OPT_32BIT | \
117 NETARM_MEM_OPT_READ_ASYNC | \
118 NETARM_MEM_OPT_WRITE_ASYNC )
119 str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
120
121 ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
122 NETARM_MEM_BAR_DRAM_SYNC | \
123 NETARM_MEM_BAR_DRAM_MUX_INT | \
124 NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
125 NETARM_MEM_BAR_DRAM_SEL | \
126 NETARM_MEM_BAR_BURST_EN | \
127 NETARM_MEM_BAR_VALID )
128 str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
129#else
130 /* we have to config FPDRAM in burst mode with smaller burst access size */
131 ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
132 NETARM_MEM_OPT_BCYC_2 | \
133 NETARM_MEM_OPT_BSIZE_16 | \
134 NETARM_MEM_OPT_WAIT_STATES(0) | \
135 NETARM_MEM_OPT_32BIT | \
136 NETARM_MEM_OPT_READ_ASYNC | \
137 NETARM_MEM_OPT_WRITE_ASYNC )
138 str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
139
140 ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
141 NETARM_MEM_BAR_DRAM_SYNC | \
142 NETARM_MEM_BAR_DRAM_MUX_INT | \
143 NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
144 NETARM_MEM_BAR_DRAM_SEL | \
145 NETARM_MEM_BAR_BURST_EN | \
146 NETARM_MEM_BAR_VALID )
147 str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
148
149#endif /* CONFIG_NETARM_NET40_REV2 */
150
151
152memsetup_cs3:
153 /*
154 * Base Addr / Option Reg 3 (EEPROM, NVRAM)
155 * ---------------------------------------------------
156 */
157#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
158 ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS3_MASK) | \
159 NETARM_MEM_OPT_BCYC_3 | \
160 NETARM_MEM_OPT_BSIZE_2 | \
161 NETARM_MEM_OPT_WAIT_STATES(10) | \
162 NETARM_MEM_OPT_8BIT | \
163 NETARM_MEM_OPT_READ_ASYNC | \
164 NETARM_MEM_OPT_WRITE_ASYNC )
165 str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
166
167 ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS3_BASE) | \
168 NETARM_MEM_BAR_DRAM_FP | \
169 NETARM_MEM_BAR_DRAM_MUX_INT | \
170 NETARM_MEM_BAR_DRAM_MUX_BAL | \
171 NETARM_MEM_BAR_VALID )
172 str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
173#else
174 /* we don't need EEPROM --> no config */
175 ldr r1, =( 0 )
176 str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
177
178 ldr r1, =( 0 )
179 str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
180#endif
181
182
183#else
184/*
185#error "missing CONFIG_MODNET50 (see your config.h)"
186*/
187#endif /* CONFIG_MODNET50 */
188
189
190memsetup_end:
191 /*
192 * manipulate address in lr and ip to match new
193 * address space
194 */
195 ldr r3, =(NETARM_MMAP_CS0_BASE)
196 mov r0, lr
197 add r0, r3, r0
198 mov lr, r0
199 mov r0, ip
200 add r0, r3, r0
201 mov ip, r0
202
203 /* everything is fine now */
204 mov pc, lr