blob: 838a0b18c38608c65b6b94b28797ce300e544d4d [file] [log] [blame]
York Sunb5b06fb2012-12-23 19:25:27 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
York Sunb5b06fb2012-12-23 19:25:27 +00005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
York Sun15672c62014-04-30 14:43:49 -070010#define CONFIG_SYS_GENERIC_BOARD
11#define CONFIG_DISPLAY_BOARDINFO
12
York Sunb5b06fb2012-12-23 19:25:27 +000013/*
14 * B4860 QDS board configuration file
15 */
16#define CONFIG_B4860QDS
17#define CONFIG_PHYS_64BIT
18
19#ifdef CONFIG_RAMBOOT_PBL
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +053020#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
21#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
22#ifndef CONFIG_NAND
York Sunb5b06fb2012-12-23 19:25:27 +000023#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
24#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +053025#else
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +053026#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
27#define CONFIG_SPL_ENV_SUPPORT
28#define CONFIG_SPL_SERIAL_SUPPORT
29#define CONFIG_SPL_FLUSH_IMAGE
30#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
31#define CONFIG_SPL_LIBGENERIC_SUPPORT
32#define CONFIG_SPL_LIBCOMMON_SUPPORT
33#define CONFIG_SPL_I2C_SUPPORT
34#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
35#define CONFIG_FSL_LAW /* Use common FSL init code */
36#define CONFIG_SYS_TEXT_BASE 0x00201000
37#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
38#define CONFIG_SPL_PAD_TO 0x40000
39#define CONFIG_SPL_MAX_SIZE 0x28000
40#define RESET_VECTOR_OFFSET 0x27FFC
41#define BOOT_PAGE_OFFSET 0x27000
42#define CONFIG_SPL_NAND_SUPPORT
43#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
44#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
45#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
46#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
47#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
48#define CONFIG_SPL_NAND_BOOT
49#ifdef CONFIG_SPL_BUILD
50#define CONFIG_SPL_SKIP_RELOCATE
51#define CONFIG_SPL_COMMON_INIT_DDR
52#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
53#define CONFIG_SYS_NO_FLASH
54#endif
55#endif
York Sunb5b06fb2012-12-23 19:25:27 +000056#endif
57
Liu Gang5870fe42013-05-07 16:30:48 +080058#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
59/* Set 1M boot space */
60#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
61#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
62 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
63#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
64#define CONFIG_SYS_NO_FLASH
65#endif
66
York Sunb5b06fb2012-12-23 19:25:27 +000067/* High Level Configuration Options */
68#define CONFIG_BOOKE
York Sunb5b06fb2012-12-23 19:25:27 +000069#define CONFIG_E500 /* BOOKE e500 family */
70#define CONFIG_E500MC /* BOOKE e500mc family */
71#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
York Sunb5b06fb2012-12-23 19:25:27 +000072#define CONFIG_MP /* support multiple processors */
73
74#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053075#define CONFIG_SYS_TEXT_BASE 0xeff40000
York Sunb5b06fb2012-12-23 19:25:27 +000076#endif
77
78#ifndef CONFIG_RESET_VECTOR_ADDRESS
79#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
80#endif
81
82#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
83#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
84#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053085#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
York Sunb5b06fb2012-12-23 19:25:27 +000086#define CONFIG_PCI /* Enable PCI/PCIE */
87#define CONFIG_PCIE1 /* PCIE controler 1 */
88#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
89#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
90
91#ifndef CONFIG_PPC_B4420
92#define CONFIG_SYS_SRIO
93#define CONFIG_SRIO1 /* SRIO port 1 */
94#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gang3a017992013-05-07 16:30:47 +080095#define CONFIG_SRIO_PCIE_BOOT_MASTER
York Sunb5b06fb2012-12-23 19:25:27 +000096#endif
97
98#define CONFIG_FSL_LAW /* Use common FSL init code */
99
100/* I2C bus multiplexer */
101#define I2C_MUX_PCA_ADDR 0x77
102
103/* VSC Crossbar switches */
104#define CONFIG_VSC_CROSSBAR
105#define I2C_CH_DEFAULT 0x8
106#define I2C_CH_VSC3316 0xc
107#define I2C_CH_VSC3308 0xd
108
109#define VSC3316_TX_ADDRESS 0x70
110#define VSC3316_RX_ADDRESS 0x71
111#define VSC3308_TX_ADDRESS 0x02
112#define VSC3308_RX_ADDRESS 0x03
113
Shaveta Leekhacb033742013-07-02 14:43:53 +0530114/* IDT clock synthesizers */
115#define CONFIG_IDT8T49N222A
116#define I2C_CH_IDT 0x9
117
118#define IDT_SERDES1_ADDRESS 0x6E
119#define IDT_SERDES2_ADDRESS 0x6C
120
Shaveta Leekha652e29b2014-04-11 14:12:40 +0530121/* Voltage monitor on channel 2*/
122#define I2C_MUX_CH_VOL_MONITOR 0xa
123#define I2C_VOL_MONITOR_ADDR 0x40
124#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
125#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
126#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
127
128#define CONFIG_ZM7300
129#define I2C_MUX_CH_DPM 0xa
130#define I2C_DPM_ADDR 0x28
131
York Sunb5b06fb2012-12-23 19:25:27 +0000132#define CONFIG_ENV_OVERWRITE
133
134#ifdef CONFIG_SYS_NO_FLASH
Liu Gang5870fe42013-05-07 16:30:48 +0800135#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
York Sunb5b06fb2012-12-23 19:25:27 +0000136#define CONFIG_ENV_IS_NOWHERE
Liu Gang5870fe42013-05-07 16:30:48 +0800137#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000138#else
139#define CONFIG_FLASH_CFI_DRIVER
140#define CONFIG_SYS_FLASH_CFI
141#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
142#endif
143
York Sunb5b06fb2012-12-23 19:25:27 +0000144#if defined(CONFIG_SPIFLASH)
145#define CONFIG_SYS_EXTRA_ENV_RELOC
146#define CONFIG_ENV_IS_IN_SPI_FLASH
147#define CONFIG_ENV_SPI_BUS 0
148#define CONFIG_ENV_SPI_CS 0
149#define CONFIG_ENV_SPI_MAX_HZ 10000000
150#define CONFIG_ENV_SPI_MODE 0
151#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
152#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
153#define CONFIG_ENV_SECT_SIZE 0x10000
154#elif defined(CONFIG_SDCARD)
155#define CONFIG_SYS_EXTRA_ENV_RELOC
156#define CONFIG_ENV_IS_IN_MMC
157#define CONFIG_SYS_MMC_ENV_DEV 0
158#define CONFIG_ENV_SIZE 0x2000
159#define CONFIG_ENV_OFFSET (512 * 1097)
160#elif defined(CONFIG_NAND)
161#define CONFIG_SYS_EXTRA_ENV_RELOC
162#define CONFIG_ENV_IS_IN_NAND
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530163#define CONFIG_ENV_SIZE 0x2000
164#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang5870fe42013-05-07 16:30:48 +0800165#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
166#define CONFIG_ENV_IS_IN_REMOTE
167#define CONFIG_ENV_ADDR 0xffe20000
168#define CONFIG_ENV_SIZE 0x2000
169#elif defined(CONFIG_ENV_IS_NOWHERE)
170#define CONFIG_ENV_SIZE 0x2000
York Sunb5b06fb2012-12-23 19:25:27 +0000171#else
172#define CONFIG_ENV_IS_IN_FLASH
173#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
174#define CONFIG_ENV_SIZE 0x2000
175#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
176#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000177
178#ifndef __ASSEMBLY__
179unsigned long get_board_sys_clk(void);
180unsigned long get_board_ddr_clk(void);
181#endif
182#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
183#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
184
185/*
186 * These can be toggled for performance analysis, otherwise use default.
187 */
188#define CONFIG_SYS_CACHE_STASHING
189#define CONFIG_BTB /* toggle branch predition */
190#define CONFIG_DDR_ECC
191#ifdef CONFIG_DDR_ECC
192#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
193#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
194#endif
195
196#define CONFIG_ENABLE_36BIT_PHYS
197
198#ifdef CONFIG_PHYS_64BIT
199#define CONFIG_ADDR_MAP
200#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
201#endif
202
203#if 0
204#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
205#endif
206#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
207#define CONFIG_SYS_MEMTEST_END 0x00400000
208#define CONFIG_SYS_ALT_MEMTEST
209#define CONFIG_PANIC_HANG /* do not reset board on panic */
210
211/*
212 * Config the L3 Cache as L3 SRAM
213 */
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530214#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
215#define CONFIG_SYS_L3_SIZE 256 << 10
216#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
217#ifdef CONFIG_NAND
218#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
219#endif
220#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
221#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
222#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
223#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
York Sunb5b06fb2012-12-23 19:25:27 +0000224
225#ifdef CONFIG_PHYS_64BIT
226#define CONFIG_SYS_DCSRBAR 0xf0000000
227#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
228#endif
229
230/* EEPROM */
Shaveta Leekha1de271b2014-09-04 16:17:09 +0530231#define CONFIG_ID_EEPROM
York Sunb5b06fb2012-12-23 19:25:27 +0000232#define CONFIG_SYS_I2C_EEPROM_NXID
233#define CONFIG_SYS_EEPROM_BUS_NUM 0
234#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
235#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
236#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
237#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
238
239/*
240 * DDR Setup
241 */
242#define CONFIG_VERY_BIG_RAM
243#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
244#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
245
246/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
247#define CONFIG_DIMM_SLOTS_PER_CTLR 1
248#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
249
250#define CONFIG_DDR_SPD
251#define CONFIG_SYS_DDR_RAW_TIMING
York Sun5614e712013-09-30 09:22:09 -0700252#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530253#ifndef CONFIG_SPL_BUILD
York Sunb5b06fb2012-12-23 19:25:27 +0000254#define CONFIG_FSL_DDR_INTERACTIVE
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530255#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000256
257#define CONFIG_SYS_SPD_BUS_NUM 0
258#define SPD_EEPROM_ADDRESS1 0x51
259#define SPD_EEPROM_ADDRESS2 0x53
260
261#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
262#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
263
264/*
265 * IFC Definitions
266 */
267#define CONFIG_SYS_FLASH_BASE 0xe0000000
268#ifdef CONFIG_PHYS_64BIT
269#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
270#else
271#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
272#endif
273
274#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
275#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
276 + 0x8000000) | \
277 CSPR_PORT_SIZE_16 | \
278 CSPR_MSEL_NOR | \
279 CSPR_V)
280#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
281#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
282 CSPR_PORT_SIZE_16 | \
283 CSPR_MSEL_NOR | \
284 CSPR_V)
285#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
286/* NOR Flash Timing Params */
287#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
288#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
Prabhakar Kushwaha4d0e6e02013-05-17 13:40:52 +0530289 FTIM0_NOR_TEADC(0x04) | \
York Sunb5b06fb2012-12-23 19:25:27 +0000290 FTIM0_NOR_TEAHC(0x20))
291#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
292 FTIM1_NOR_TRAD_NOR(0x1A) |\
293 FTIM1_NOR_TSEQRAD_NOR(0x13))
294#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
295 FTIM2_NOR_TCH(0x0E) | \
296 FTIM2_NOR_TWPH(0x0E) | \
297 FTIM2_NOR_TWP(0x1c))
298#define CONFIG_SYS_NOR_FTIM3 0x0
299
300#define CONFIG_SYS_FLASH_QUIET_TEST
301#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
302
303#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
304#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
305#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
306#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
307
308#define CONFIG_SYS_FLASH_EMPTY_INFO
309#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
310 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
311
312#define CONFIG_FSL_QIXIS /* use common QIXIS code */
313#define CONFIG_FSL_QIXIS_V2
314#define QIXIS_BASE 0xffdf0000
315#ifdef CONFIG_PHYS_64BIT
316#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
317#else
318#define QIXIS_BASE_PHYS QIXIS_BASE
319#endif
320#define QIXIS_LBMAP_SWITCH 0x01
321#define QIXIS_LBMAP_MASK 0x0f
322#define QIXIS_LBMAP_SHIFT 0
323#define QIXIS_LBMAP_DFLTBANK 0x00
324#define QIXIS_LBMAP_ALTBANK 0x02
325#define QIXIS_RST_CTL_RESET 0x31
326#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
327#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
328#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
329
330#define CONFIG_SYS_CSPR3_EXT (0xf)
331#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
332 | CSPR_PORT_SIZE_8 \
333 | CSPR_MSEL_GPCM \
334 | CSPR_V)
335#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
336#define CONFIG_SYS_CSOR3 0x0
337/* QIXIS Timing parameters for IFC CS3 */
338#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
339 FTIM0_GPCM_TEADC(0x0e) | \
340 FTIM0_GPCM_TEAHC(0x0e))
341#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
342 FTIM1_GPCM_TRAD(0x1f))
343#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800344 FTIM2_GPCM_TCH(0x8) | \
York Sunb5b06fb2012-12-23 19:25:27 +0000345 FTIM2_GPCM_TWP(0x1f))
346#define CONFIG_SYS_CS3_FTIM3 0x0
347
348/* NAND Flash on IFC */
349#define CONFIG_NAND_FSL_IFC
York Sunab13ad52013-12-17 11:21:09 -0800350#define CONFIG_SYS_NAND_MAX_ECCPOS 256
351#define CONFIG_SYS_NAND_MAX_OOBFREE 2
York Sunb5b06fb2012-12-23 19:25:27 +0000352#define CONFIG_SYS_NAND_BASE 0xff800000
353#ifdef CONFIG_PHYS_64BIT
354#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
355#else
356#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
357#endif
358
359#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
360#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
361 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
362 | CSPR_MSEL_NAND /* MSEL = NAND */ \
363 | CSPR_V)
364#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
365
366#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
367 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
368 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
369 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
370 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
371 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
372 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
373
374#define CONFIG_SYS_NAND_ONFI_DETECTION
375
376/* ONFI NAND Flash mode0 Timing Params */
377#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
378 FTIM0_NAND_TWP(0x18) | \
379 FTIM0_NAND_TWCHT(0x07) | \
380 FTIM0_NAND_TWH(0x0a))
381#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
382 FTIM1_NAND_TWBE(0x39) | \
383 FTIM1_NAND_TRR(0x0e) | \
384 FTIM1_NAND_TRP(0x18))
385#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
386 FTIM2_NAND_TREH(0x0a) | \
387 FTIM2_NAND_TWHRE(0x1e))
388#define CONFIG_SYS_NAND_FTIM3 0x0
389
390#define CONFIG_SYS_NAND_DDR_LAW 11
391
392#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
393#define CONFIG_SYS_MAX_NAND_DEVICE 1
394#define CONFIG_MTD_NAND_VERIFY_WRITE
395#define CONFIG_CMD_NAND
396
397#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
398
399#if defined(CONFIG_NAND)
400#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
401#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
402#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
403#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
404#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
405#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
406#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
407#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
408#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
409#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
410#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
411#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
412#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
413#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
414#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
415#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
416#else
417#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
418#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
419#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
420#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
421#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
422#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
423#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
424#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
425#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
426#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
427#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
428#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
429#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
430#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
431#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
432#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
433#endif
434#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
435#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
436#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
437#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
438#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
439#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
440#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
441#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
442
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530443#ifdef CONFIG_SPL_BUILD
444#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
445#else
446#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
447#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000448
449#if defined(CONFIG_RAMBOOT_PBL)
450#define CONFIG_SYS_RAMBOOT
451#endif
452
453#define CONFIG_BOARD_EARLY_INIT_R
454#define CONFIG_MISC_INIT_R
455
456#define CONFIG_HWCONFIG
457
458/* define to use L1 as initial stack */
459#define CONFIG_L1_INIT_RAM
460#define CONFIG_SYS_INIT_RAM_LOCK
461#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
462#ifdef CONFIG_PHYS_64BIT
463#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
464#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
465/* The assembler doesn't like typecast */
466#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
467 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
468 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
469#else
470#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
471#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
472#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
473#endif
474#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
475
476#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
477 GENERATED_GBL_DATA_SIZE)
478#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
479
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530480#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
York Sunb5b06fb2012-12-23 19:25:27 +0000481#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
482
483/* Serial Port - controlled on board with jumper J8
484 * open - index 2
485 * shorted - index 1
486 */
487#define CONFIG_CONS_INDEX 1
488#define CONFIG_SYS_NS16550
489#define CONFIG_SYS_NS16550_SERIAL
490#define CONFIG_SYS_NS16550_REG_SIZE 1
491#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
492
493#define CONFIG_SYS_BAUDRATE_TABLE \
494 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
495
496#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
497#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
498#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
499#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
500#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530501#ifndef CONFIG_SPL_BUILD
York Sunb5b06fb2012-12-23 19:25:27 +0000502#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530503#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000504
505
506/* Use the HUSH parser */
507#define CONFIG_SYS_HUSH_PARSER
508#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
509
510/* pass open firmware flat tree */
511#define CONFIG_OF_LIBFDT
512#define CONFIG_OF_BOARD_SETUP
513#define CONFIG_OF_STDOUT_VIA_ALIAS
514
515/* new uImage format support */
516#define CONFIG_FIT
517#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
518
519/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200520#define CONFIG_SYS_I2C
521#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
522#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
523#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
524#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
525#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
526#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
527#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
York Sunb5b06fb2012-12-23 19:25:27 +0000528
529/*
530 * RTC configuration
531 */
532#define RTC
533#define CONFIG_RTC_DS3231 1
534#define CONFIG_SYS_I2C_RTC_ADDR 0x68
535
536/*
537 * RapidIO
538 */
539#ifdef CONFIG_SYS_SRIO
540#ifdef CONFIG_SRIO1
541#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
542#ifdef CONFIG_PHYS_64BIT
543#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
544#else
545#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
546#endif
547#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
548#endif
549
550#ifdef CONFIG_SRIO2
551#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
552#ifdef CONFIG_PHYS_64BIT
553#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
554#else
555#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
556#endif
557#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
558#endif
559#endif
560
561/*
562 * for slave u-boot IMAGE instored in master memory space,
563 * PHYS must be aligned based on the SIZE
564 */
Liu Gange4911812014-05-15 14:30:34 +0800565#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
566#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
567#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
568#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
York Sunb5b06fb2012-12-23 19:25:27 +0000569/*
570 * for slave UCODE and ENV instored in master memory space,
571 * PHYS must be aligned based on the SIZE
572 */
Liu Gange4911812014-05-15 14:30:34 +0800573#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
York Sunb5b06fb2012-12-23 19:25:27 +0000574#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
575#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
576
577/* slave core release by master*/
578#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
579#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
580
581/*
582 * SRIO_PCIE_BOOT - SLAVE
583 */
584#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
585#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
586#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
587 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
588#endif
589
590/*
591 * eSPI - Enhanced SPI
592 */
593#define CONFIG_FSL_ESPI
594#define CONFIG_SPI_FLASH
595#define CONFIG_SPI_FLASH_SST
596#define CONFIG_CMD_SF
597#define CONFIG_SF_DEFAULT_SPEED 10000000
598#define CONFIG_SF_DEFAULT_MODE 0
599
600/*
Shaveta Leekha6eaeba22013-03-25 07:40:24 +0000601 * MAPLE
602 */
603#ifdef CONFIG_PHYS_64BIT
604#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
605#else
606#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
607#endif
608
609/*
York Sunb5b06fb2012-12-23 19:25:27 +0000610 * General PCI
611 * Memory space is mapped 1-1, but I/O space must start from 0.
612 */
613
614/* controller 1, direct to uli, tgtid 3, Base address 20000 */
615#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
616#ifdef CONFIG_PHYS_64BIT
617#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
618#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
619#else
620#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
621#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
622#endif
623#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
624#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
625#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
626#ifdef CONFIG_PHYS_64BIT
627#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
628#else
629#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
630#endif
631#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
632
633/* Qman/Bman */
634#ifndef CONFIG_NOBQFMAN
635#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
636#define CONFIG_SYS_BMAN_NUM_PORTALS 25
637#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
638#ifdef CONFIG_PHYS_64BIT
639#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
640#else
641#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
642#endif
643#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500644#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
645#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
646#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
647#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
648#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
649 CONFIG_SYS_BMAN_CENA_SIZE)
650#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
651#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
York Sunb5b06fb2012-12-23 19:25:27 +0000652#define CONFIG_SYS_QMAN_NUM_PORTALS 25
653#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
654#ifdef CONFIG_PHYS_64BIT
655#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
656#else
657#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
658#endif
659#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500660#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
661#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
662#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
663#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
664#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
665 CONFIG_SYS_QMAN_CENA_SIZE)
666#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
667#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
York Sunb5b06fb2012-12-23 19:25:27 +0000668
669#define CONFIG_SYS_DPAA_FMAN
670
Minghuan Lian0795eff2013-07-03 18:32:41 +0800671#define CONFIG_SYS_DPAA_RMAN
672
York Sunb5b06fb2012-12-23 19:25:27 +0000673/* Default address of microcode for the Linux Fman driver */
674#if defined(CONFIG_SPIFLASH)
675/*
676 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
677 * env, so we got 0x110000.
678 */
679#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800680#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
York Sunb5b06fb2012-12-23 19:25:27 +0000681#elif defined(CONFIG_SDCARD)
682/*
683 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
684 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
685 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
686 */
687#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800688#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
York Sunb5b06fb2012-12-23 19:25:27 +0000689#elif defined(CONFIG_NAND)
690#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530691#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang5870fe42013-05-07 16:30:48 +0800692#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
693/*
694 * Slave has no ucode locally, it can fetch this from remote. When implementing
695 * in two corenet boards, slave's ucode could be stored in master's memory
696 * space, the address can be mapped from slave TLB->slave LAW->
697 * slave SRIO or PCIE outbound window->master inbound window->
698 * master LAW->the ucode address in master's memory space.
699 */
700#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800701#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
York Sunb5b06fb2012-12-23 19:25:27 +0000702#else
703#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800704#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
York Sunb5b06fb2012-12-23 19:25:27 +0000705#endif
706#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
707#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
708#endif /* CONFIG_NOBQFMAN */
709
710#ifdef CONFIG_SYS_DPAA_FMAN
711#define CONFIG_FMAN_ENET
712#define CONFIG_PHYLIB_10G
713#define CONFIG_PHY_VITESSE
714#define CONFIG_PHY_TERANETICS
715#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
716#define SGMII_CARD_PORT2_PHY_ADDR 0x10
717#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
718#define SGMII_CARD_PORT4_PHY_ADDR 0x11
719#endif
720
721#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000722#define CONFIG_PCI_INDIRECT_BRIDGE
York Sunb5b06fb2012-12-23 19:25:27 +0000723#define CONFIG_NET_MULTI
724#define CONFIG_PCI_PNP /* do pci plug-and-play */
725#define CONFIG_E1000
726
727#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
728#define CONFIG_DOS_PARTITION
729#endif /* CONFIG_PCI */
730
731#ifdef CONFIG_FMAN_ENET
Shaveta Leekhaf1d80742014-11-12 16:00:22 +0530732#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
733#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
Suresh Gupta16d88f42013-03-25 07:40:13 +0000734
735/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
736#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
737#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
738
York Sunb5b06fb2012-12-23 19:25:27 +0000739
740#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
741#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
742#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
743#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
744
745#define CONFIG_MII /* MII PHY management */
746#define CONFIG_ETHPRIME "FM1@DTSEC1"
747#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
748#endif
749
Shaohui Xieb24f6d42014-11-13 11:27:49 +0800750#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
751
York Sunb5b06fb2012-12-23 19:25:27 +0000752/*
753 * Environment
754 */
755#define CONFIG_LOADS_ECHO /* echo on for serial download */
756#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
757
758/*
759 * Command line configuration.
760 */
761#include <config_cmd_default.h>
762
763#define CONFIG_CMD_DATE
764#define CONFIG_CMD_DHCP
765#define CONFIG_CMD_EEPROM
766#define CONFIG_CMD_ELF
767#define CONFIG_CMD_ERRATA
768#define CONFIG_CMD_GREPENV
769#define CONFIG_CMD_IRQ
770#define CONFIG_CMD_I2C
771#define CONFIG_CMD_MII
772#define CONFIG_CMD_PING
773#define CONFIG_CMD_REGINFO
774#define CONFIG_CMD_SETEXPR
775
776#ifdef CONFIG_PCI
777#define CONFIG_CMD_PCI
778#define CONFIG_CMD_NET
779#endif
780
Ruchika Gupta737537e2014-10-15 11:35:31 +0530781/* Hash command with SHA acceleration supported in hardware */
782#ifdef CONFIG_FSL_CAAM
783#define CONFIG_CMD_HASH
784#define CONFIG_SHA_HW_ACCEL
785#endif
786
York Sunb5b06fb2012-12-23 19:25:27 +0000787/*
788* USB
789*/
790#define CONFIG_HAS_FSL_DR_USB
791
792#ifdef CONFIG_HAS_FSL_DR_USB
793#define CONFIG_USB_EHCI
794
795#ifdef CONFIG_USB_EHCI
796#define CONFIG_CMD_USB
797#define CONFIG_USB_STORAGE
798#define CONFIG_USB_EHCI_FSL
799#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
800#define CONFIG_CMD_EXT2
801#endif
802#endif
803
804/*
805 * Miscellaneous configurable options
806 */
807#define CONFIG_SYS_LONGHELP /* undef to save memory */
808#define CONFIG_CMDLINE_EDITING /* Command-line editing */
809#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
810#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
York Sunb5b06fb2012-12-23 19:25:27 +0000811#ifdef CONFIG_CMD_KGDB
812#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
813#else
814#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
815#endif
816#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
817#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
818#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
York Sunb5b06fb2012-12-23 19:25:27 +0000819
820/*
821 * For booting Linux, the board info and command line data
822 * have to be in the first 64 MB of memory, since this is
823 * the maximum mapped by the Linux kernel during initialization.
824 */
825#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
826#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
827
828#ifdef CONFIG_CMD_KGDB
829#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
York Sunb5b06fb2012-12-23 19:25:27 +0000830#endif
831
832/*
833 * Environment Configuration
834 */
835#define CONFIG_ROOTPATH "/opt/nfsroot"
836#define CONFIG_BOOTFILE "uImage"
837#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
838
839/* default location for tftp and bootm */
840#define CONFIG_LOADADDR 1000000
841
842#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
843
844#define CONFIG_BAUDRATE 115200
845
846#define __USB_PHY_TYPE ulpi
847
Shaveta Leekha38e0e152014-09-04 11:43:57 +0530848#ifdef CONFIG_PPC_B4860
849#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
850 "bank_intlv=cs0_cs1;" \
851 "en_cpc:cpc2;"
852#else
853#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
854#endif
855
York Sunb5b06fb2012-12-23 19:25:27 +0000856#define CONFIG_EXTRA_ENV_SETTINGS \
Shaveta Leekha38e0e152014-09-04 11:43:57 +0530857 HWCONFIG \
York Sunb5b06fb2012-12-23 19:25:27 +0000858 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
859 "netdev=eth0\0" \
860 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
861 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
862 "tftpflash=tftpboot $loadaddr $uboot && " \
863 "protect off $ubootaddr +$filesize && " \
864 "erase $ubootaddr +$filesize && " \
865 "cp.b $loadaddr $ubootaddr $filesize && " \
866 "protect on $ubootaddr +$filesize && " \
867 "cmp.b $loadaddr $ubootaddr $filesize\0" \
868 "consoledev=ttyS0\0" \
869 "ramdiskaddr=2000000\0" \
870 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
871 "fdtaddr=c00000\0" \
872 "fdtfile=b4860qds/b4860qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500873 "bdev=sda3\0"
York Sunb5b06fb2012-12-23 19:25:27 +0000874
875/* For emulation this causes u-boot to jump to the start of the proof point
876 app code automatically */
877#define CONFIG_PROOF_POINTS \
878 "setenv bootargs root=/dev/$bdev rw " \
879 "console=$consoledev,$baudrate $othbootargs;" \
880 "cpu 1 release 0x29000000 - - -;" \
881 "cpu 2 release 0x29000000 - - -;" \
882 "cpu 3 release 0x29000000 - - -;" \
883 "cpu 4 release 0x29000000 - - -;" \
884 "cpu 5 release 0x29000000 - - -;" \
885 "cpu 6 release 0x29000000 - - -;" \
886 "cpu 7 release 0x29000000 - - -;" \
887 "go 0x29000000"
888
889#define CONFIG_HVBOOT \
890 "setenv bootargs config-addr=0x60000000; " \
891 "bootm 0x01000000 - 0x00f00000"
892
893#define CONFIG_ALU \
894 "setenv bootargs root=/dev/$bdev rw " \
895 "console=$consoledev,$baudrate $othbootargs;" \
896 "cpu 1 release 0x01000000 - - -;" \
897 "cpu 2 release 0x01000000 - - -;" \
898 "cpu 3 release 0x01000000 - - -;" \
899 "cpu 4 release 0x01000000 - - -;" \
900 "cpu 5 release 0x01000000 - - -;" \
901 "cpu 6 release 0x01000000 - - -;" \
902 "cpu 7 release 0x01000000 - - -;" \
903 "go 0x01000000"
904
905#define CONFIG_LINUX \
906 "setenv bootargs root=/dev/ram rw " \
907 "console=$consoledev,$baudrate $othbootargs;" \
908 "setenv ramdiskaddr 0x02000000;" \
909 "setenv fdtaddr 0x00c00000;" \
910 "setenv loadaddr 0x1000000;" \
911 "bootm $loadaddr $ramdiskaddr $fdtaddr"
912
913#define CONFIG_HDBOOT \
914 "setenv bootargs root=/dev/$bdev rw " \
915 "console=$consoledev,$baudrate $othbootargs;" \
916 "tftp $loadaddr $bootfile;" \
917 "tftp $fdtaddr $fdtfile;" \
918 "bootm $loadaddr - $fdtaddr"
919
920#define CONFIG_NFSBOOTCOMMAND \
921 "setenv bootargs root=/dev/nfs rw " \
922 "nfsroot=$serverip:$rootpath " \
923 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
924 "console=$consoledev,$baudrate $othbootargs;" \
925 "tftp $loadaddr $bootfile;" \
926 "tftp $fdtaddr $fdtfile;" \
927 "bootm $loadaddr - $fdtaddr"
928
929#define CONFIG_RAMBOOTCOMMAND \
930 "setenv bootargs root=/dev/ram rw " \
931 "console=$consoledev,$baudrate $othbootargs;" \
932 "tftp $ramdiskaddr $ramdiskfile;" \
933 "tftp $loadaddr $bootfile;" \
934 "tftp $fdtaddr $fdtfile;" \
935 "bootm $loadaddr $ramdiskaddr $fdtaddr"
936
937#define CONFIG_BOOTCOMMAND CONFIG_LINUX
938
York Sunb5b06fb2012-12-23 19:25:27 +0000939#include <asm/fsl_secure_boot.h>
York Sunb5b06fb2012-12-23 19:25:27 +0000940
Ruchika Gupta789490b2014-10-07 15:48:46 +0530941#ifdef CONFIG_SECURE_BOOT
942#define CONFIG_CMD_BLOB
943#endif
944
York Sunb5b06fb2012-12-23 19:25:27 +0000945#endif /* __CONFIG_H */