blob: 31a93c87de8bbc5f4e5983068f2691d150a45cc7 [file] [log] [blame]
Jon Smirlc9969942009-06-14 18:21:28 -04001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Eric Schumann, Phytec Messatechnik GmbH
7 *
8 * (C) Copyright 2009
9 * Jon Smirl <jonsmirl@gmail.com>
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Jon Smirlc9969942009-06-14 18:21:28 -040012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
18
19/*-----------------------------------------------------------------------------
20High Level Configuration Options
21(easy to change)
22-----------------------------------------------------------------------------*/
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090023#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
Jon Smirlc9969942009-06-14 18:21:28 -040024#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
25#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
26 /* FEC configuration and IDE */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027
28/*
29 * Valid values for CONFIG_SYS_TEXT_BASE are:
30 * 0xFFF00000 boot high (standard configuration)
31 * 0xFF000000 boot low
32 * 0x00100000 boot from RAM (for testing only)
33 */
34#ifndef CONFIG_SYS_TEXT_BASE
35#define CONFIG_SYS_TEXT_BASE 0xFFF00000
36#endif
37
Jon Smirlc9969942009-06-14 18:21:28 -040038#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
Jon Smirlc9969942009-06-14 18:21:28 -040039
40/*-----------------------------------------------------------------------------
41Serial console configuration
42-----------------------------------------------------------------------------*/
43#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
44 /*define gps port conf. */
45 /* register later on to */
46 /*enable UART function! */
47#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
49
50/*
51 * Command line configuration.
52 */
53#include <config_cmd_default.h>
54
55#define CONFIG_CMD_DATE
56#define CONFIG_CMD_DHCP
57#define CONFIG_CMD_EEPROM
58#define CONFIG_CMD_I2C
59#define CONFIG_CMD_JFFS2
60#define CONFIG_CMD_MII
61#define CONFIG_CMD_NFS
62#define CONFIG_CMD_PCI
63
64#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
65
Wolfgang Denk14d0a022010-10-07 21:51:12 +020066#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
Jon Smirlc9969942009-06-14 18:21:28 -040067#define CONFIG_SYS_LOWBOOT 1
68#endif
69/* RAMBOOT will be defined automatically in memory section */
70
71#define CONFIG_JFFS2_CMDLINE
72#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
73#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
74 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
75
76/*-----------------------------------------------------------------------------
77Autobooting
78-----------------------------------------------------------------------------*/
79#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
80#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
81 /* even with bootdelay=0 */
82#undef CONFIG_BOOTARGS
83
84
85#define CONFIG_PREBOOT "echo;" \
86 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
87 "mount root filesystem over NFS;" \
88 "echo"
89
90#define CONFIG_EXTRA_ENV_SETTINGS \
91 "netdev=eth0\0" \
92 "uimage=uImage-pcm030\0" \
93 "oftree=oftree-pcm030.dtb\0" \
94 "jffs2=root-pcm030.jffs2\0" \
95 "uboot=u-boot-pcm030.bin\0" \
96 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
97 " $(mtdparts) rw\0" \
98 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
99 " rootfstype=jffs2\0" \
100 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
101 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
102 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
103 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
104 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
105 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
106 "0xfff40000\0" \
107 " cp.b 0x400000 0xff040000 $(filesize)\0" \
108 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
109 "cp.b 0x400000 0xff200000 $(filesize)\0" \
110 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
111 " cp.b 0x400000 0xfff40000 $(filesize)\0" \
112 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
113 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \
114 "unlock=yes\0" \
115 ""
116
117#define CONFIG_BOOTCOMMAND "run bcmd_flash"
118
119/*--------------------------------------------------------------------------
120IPB Bus clocking configuration.
121 ---------------------------------------------------------------------------*/
122#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
123
124/*-------------------------------------------------------------------------
125 * PCI Mapping:
126 * 0x40000000 - 0x4fffffff - PCI Memory
127 * 0x50000000 - 0x50ffffff - PCI IO Space
128 * -----------------------------------------------------------------------*/
129#define CONFIG_PCI 1
130#define CONFIG_PCI_PNP 1
131#define CONFIG_PCI_SCAN_SHOW 1
132#define CONFIG_PCI_MEM_BUS 0x40000000
133#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
134#define CONFIG_PCI_MEM_SIZE 0x10000000
135#define CONFIG_PCI_IO_BUS 0x50000000
136#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
137#define CONFIG_PCI_IO_SIZE 0x01000000
138#define CONFIG_SYS_XLB_PIPELINING 1
139
140/*---------------------------------------------------------------------------
141 I2C configuration
142---------------------------------------------------------------------------*/
143#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
144#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
145#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
146#define CONFIG_SYS_I2C_SLAVE 0x7F
147
148/*---------------------------------------------------------------------------
149 EEPROM CAT24WC32 configuration
150---------------------------------------------------------------------------*/
151#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
152#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
153#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
154#define CONFIG_SYS_EEPROM_SIZE 2048
155#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
156#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
157
158/*---------------------------------------------------------------------------
159RTC configuration
160---------------------------------------------------------------------------*/
161#define RTC
162#define CONFIG_RTC_PCF8563 1
163#define CONFIG_SYS_I2C_RTC_ADDR 0x51
164
165/*---------------------------------------------------------------------------
166 Flash configuration
167---------------------------------------------------------------------------*/
168
169#define CONFIG_SYS_FLASH_BASE 0xff000000
170#define CONFIG_SYS_FLASH_SIZE 0x01000000
171#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
172
173#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
174#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
175#define CONFIG_SYS_FLASH_EMPTY_INFO
176#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
177#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
178 /* (= chip selects) */
179#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
180
181/*
182 * Use also hardware protection. This seems required, as the BDI uses
183 * hardware protection. Without this, U-Boot can't work with this sectors,
184 * as its protection is software only by default
185 */
186#define CONFIG_SYS_FLASH_PROTECTION 1
187
188/*---------------------------------------------------------------------------
189 Environment settings
190---------------------------------------------------------------------------*/
191
192/* pcm030 ships with environment is EEPROM by default */
193#define CONFIG_ENV_IS_IN_EEPROM 1
194#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
195 /*beginning of the EEPROM */
196#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
197
198#define CONFIG_ENV_OVERWRITE 1
199
200/*-----------------------------------------------------------------------------
201 Memory map
202-----------------------------------------------------------------------------*/
203#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
204 /* bootloader or debugger config */
205#define CONFIG_SYS_SDRAM_BASE 0x00000000
206#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
207/* Use SRAM until RAM will be available */
208#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200209#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */
Jon Smirlc9969942009-06-14 18:21:28 -0400210 /* area in DPRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200211#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200212 GENERATED_GBL_DATA_SIZE)
Jon Smirlc9969942009-06-14 18:21:28 -0400213#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
214
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200215#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jon Smirlc9969942009-06-14 18:21:28 -0400216#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
217# define CONFIG_SYS_RAMBOOT 1
218#endif
219
220#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
221#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
222#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
223
224/*-----------------------------------------------------------------------------
225 Ethernet configuration
226-----------------------------------------------------------------------------*/
227#define CONFIG_MPC5xxx_FEC 1
228#define CONFIG_MPC5xxx_FEC_MII100
229#define CONFIG_PHY_ADDR 0x01
230
231/*---------------------------------------------------------------------------
232 GPIO configuration
233 ---------------------------------------------------------------------------*/
234
235/* GPIO port configuration
236 *
237 * Pin mapping:
238 *
239 * [29:31] = 01x
240 * PSC1_0 -> AC97 SDATA out
241 * PSC1_1 -> AC97 SDTA in
242 * PSC1_2 -> AC97 SYNC out
243 * PSC1_3 -> AC97 bitclock out
244 * PSC1_4 -> AC97 reset out
245 *
246 * [25:27] = 001
247 * PSC2_0 -> CAN 1 Tx out
248 * PSC2_1 -> CAN 1 Rx in
249 * PSC2_2 -> CAN 2 Tx out
250 * PSC2_3 -> CAN 2 Rx in
251 * PSC2_4 -> GPIO (claimed for ATA reset, active low)
252 *
253 *
254 * [20:23] = 1100
255 * PSC3_0 -> UART Tx out
256 * PSC3_1 -> UART Rx in
257 * PSC3_2 -> UART RTS (in/out FIXME)
258 * PSC3_3 -> UART CTS (in/out FIXME)
259 * PSC3_4 -> LocalPlus Bus CS6 \
260 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
261 * PSC3_6 -> dedicated SPI MOSI out (master case)
262 * PSC3_7 -> dedicated SPI MISO in (master case)
263 * PSC3_8 -> dedicated SPI SS out (master case)
264 * PSC3_9 -> dedicated SPI CLK out (master case)
265 *
266 * [18:19] = 01
267 * USB_0 -> USB OE out
268 * USB_1 -> USB Tx- out
269 * USB_2 -> USB Tx+ out
270 * USB_3 -> USB RxD (in/out FIXME)
271 * USB_4 -> USB Rx+ in
272 * USB_5 -> USB Rx- in
273 * USB_6 -> USB PortPower out
274 * USB_7 -> USB speed out
275 * USB_8 -> USB suspend (in/out FIXME)
276 * USB_9 -> USB overcurrent in
277 *
278 * [17] = 0
279 * USB differential mode
280 *
281 * [16] = 0
282 * PCI enabled
283 *
284 * [12:15] = 0101
285 * ETH_0 -> ETH Txen
286 * ETH_1 -> ETH TxD0
287 * ETH_2 -> ETH TxD1
288 * ETH_3 -> ETH TxD2
289 * ETH_4 -> ETH TxD3
290 * ETH_5 -> ETH Txerr
291 * ETH_6 -> ETH MDC
292 * ETH_7 -> ETH MDIO
293 * ETH_8 -> ETH RxDv
294 * ETH_9 -> ETH RxCLK
295 * ETH_10 -> ETH Collision
296 * ETH_11 -> ETH TxD
297 * ETH_12 -> ETH RxD0
298 * ETH_13 -> ETH RxD1
299 * ETH_14 -> ETH RxD2
300 * ETH_15 -> ETH RxD3
301 * ETH_16 -> ETH Rxerr
302 * ETH_17 -> ETH CRS
303 *
304 * [9:11] = 101
305 * PSC6_0 -> UART RxD in
306 * PSC6_1 -> UART CTS (in/out FIXME)
307 * PSC6_2 -> UART TxD out
308 * PSC6_3 -> UART RTS (in/out FIXME)
309 *
310 * [2:3/6:7] = 00/11
311 * TMR_0 -> ATA_CS0 out
312 * TMR_1 -> ATA_CS1 out
313 * TMR_2 -> GPIO
314 * TMR_3 -> GPIO
315 * TMR_4 -> GPIO
316 * TMR_5 -> GPIO
317 * TMR_6 -> GPIO
318 * TMR_7 -> GPIO
319 * I2C_0 -> I2C 1 Clock out
320 * I2C_1 -> I2C 1 IO in/out
321 * I2C_2 -> I2C 2 Clock out
322 * I2C_3 -> I2C 2 IO in/out
323 *
324 * [4] = 1
325 * PSC3_5 is used as CS7
326 *
327 * [5] = 1
328 * PSC3_4 is used as CS6
329 *
330 * [1] = 0
331 * gpio_wkup_7 is GPIO
332 *
333 * [0] = 0
334 * gpio_wkup_6 is GPIO
335 *
336 */
337#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
338
339/*-----------------------------------------------------------------------------
340 Miscellaneous configurable options
341-------------------------------------------------------------------------------*/
342#define CONFIG_SYS_LONGHELP /* undef to save memory */
343#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
344
345#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
346
347#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
348#if defined(CONFIG_CMD_KGDB)
349#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
350#endif
351
352#if defined(CONFIG_CMD_KGDB)
353#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
354#else
355#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
356#endif
357#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
358 /* Print Buffer Size */
359#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
360#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
361
362#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
363#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
364
365#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
Jon Smirlc9969942009-06-14 18:21:28 -0400366
367#define CONFIG_DISPLAY_BOARDINFO 1
368
369/*-----------------------------------------------------------------------------
370 Various low-level settings
371-----------------------------------------------------------------------------*/
372#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
373#define CONFIG_SYS_HID0_FINAL HID0_ICE
374
375/* no burst access on the LPB */
376#define CONFIG_SYS_CS_BURST 0x00000000
377/* one deadcycle for the 33MHz statemachine */
378#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
379/* one additional waitstate for the 33MHz statemachine */
380#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
381#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
382#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
383
384#define CONFIG_SYS_RESET_ADDRESS 0xff000000
385
386/*-----------------------------------------------------------------------
387 * USB stuff
388 *-----------------------------------------------------------------------
389 */
390#define CONFIG_USB_CLOCK 0x0001BBBB
391#define CONFIG_USB_CONFIG 0x00001000
392
393/*---------------------------------------------------------------------------
394 IDE/ATA stuff Supports IDE harddisk
395----------------------------------------------------------------------------*/
396
397#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
398#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
399#undef CONFIG_IDE_LED /* LED for ide not supported */
400#define CONFIG_SYS_ATA_CS_ON_TIMER01
401#define CONFIG_IDE_RESET 1 /* reset for ide supported */
402#define CONFIG_IDE_PREINIT
403#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
404#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
405#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
406#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
407/* Offset for data I/O */
408#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
409/* Offset for normal register accesses */
410#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
411/* Offset for alternate registers */
412#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
413/* Interval between registers */
414#define CONFIG_SYS_ATA_STRIDE 4
415#define CONFIG_ATAPI 1
416
417/* we enable IDE and FAT support, so we also need partition support */
418#define CONFIG_DOS_PARTITION 1
419
420/* USB */
421#define CONFIG_USB_OHCI
422#define CONFIG_USB_STORAGE
423
424/* pass open firmware flat tree */
425#define CONFIG_OF_LIBFDT 1
426#define CONFIG_OF_BOARD_SETUP 1
427
428#define OF_CPU "PowerPC,5200@0"
429#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
430#define OF_SOC "soc5200@f0000000"
431#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
432
433#endif /* __CONFIG_H */