blob: df10c0e6aa37805d5087eae592b75aaffd586916 [file] [log] [blame]
Stefan Roese7644f162005-09-22 09:16:57 +02001/*
2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denkf013dac2005-12-04 00:40:34 +010015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Stefan Roese7644f162005-09-22 09:16:57 +020016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
27#include <malloc.h>
28
29int board_early_init_f (void)
30{
31 unsigned long cntrl0Reg;
32
33 /*
Stefan Roeseea339202005-11-08 09:00:09 +010034 * Setup GPIO pins (CS4+CS7 as GPIO)
Stefan Roese7644f162005-09-22 09:16:57 +020035 */
36 cntrl0Reg = mfdcr(cntrl0);
Stefan Roeseea339202005-11-08 09:00:09 +010037 mtdcr(cntrl0, cntrl0Reg | 0x00900000);
Stefan Roese7644f162005-09-22 09:16:57 +020038
Wolfgang Denkf013dac2005-12-04 00:40:34 +010039 /* set output pins to high */
40 out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED);
41 /* INTA# is open drain */
Stefan Roeseea339202005-11-08 09:00:09 +010042 out32(GPIO0_ODR, CFG_INTA_FAKE);
Wolfgang Denkf013dac2005-12-04 00:40:34 +010043 /* setup for output */
Stefan Roeseea339202005-11-08 09:00:09 +010044 out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP);
Stefan Roese7644f162005-09-22 09:16:57 +020045
46 /*
47 * IRQ 0-15 405GP internally generated; active high; level sensitive
48 * IRQ 16 405GP internally generated; active low; level sensitive
49 * IRQ 17-24 RESERVED
50 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
51 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
52 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
53 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
54 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
55 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
56 * IRQ 31 (EXT IRQ 6) unused
57 */
Wolfgang Denkf013dac2005-12-04 00:40:34 +010058 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
59 mtdcr(uicer, 0x00000000); /* disable all ints */
60 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
61 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
Stefan Roese7644f162005-09-22 09:16:57 +020062
Wolfgang Denkf013dac2005-12-04 00:40:34 +010063 mtdcr(uictr, 0x10000000); /* set int trigger levels */
64 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
65 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
Stefan Roese7644f162005-09-22 09:16:57 +020066
67 return 0;
68}
69
70
71int misc_init_f (void)
72{
73 return 0; /* dummy implementation */
74}
75
76
77int misc_init_r (void)
78{
79 DECLARE_GLOBAL_DATA_PTR;
80 unsigned long cntrl0Reg;
81
82 /* adjust flash start and offset */
83 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
84 gd->bd->bi_flashoffset = 0;
85
86 /*
87 * Select cts (and not dsr) on uart1
88 */
89 cntrl0Reg = mfdcr(cntrl0);
90 mtdcr(cntrl0, cntrl0Reg | 0x00001000);
91
92 return (0);
93}
94
95
96/*
97 * Check Board Identity:
98 */
99int checkboard (void)
100{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200101 char str[64];
Stefan Roese7644f162005-09-22 09:16:57 +0200102 int i = getenv_r ("serial#", str, sizeof(str));
103
104 puts ("Board: ");
105
106 if (i == -1) {
107 puts ("### No HW ID - assuming CPCI2DP");
108 } else {
109 puts(str);
110 }
111
112 printf(" (Ver 1.0)");
113
114 putc ('\n');
115
116 return 0;
117}
118
119/* ------------------------------------------------------------------------- */
120
121long int initdram (int board_type)
122{
123 unsigned long val;
124
125 mtdcr(memcfga, mem_mb0cf);
126 val = mfdcr(memcfgd);
127
128 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
129}
130
131/* ------------------------------------------------------------------------- */
132
133int testdram (void)
134{
135 /* TODO: XXX XXX XXX */
136 printf ("test: 64 MB - ok\n");
137
138 return (0);
139}
140
141/* ------------------------------------------------------------------------- */
142
143#if defined(CFG_EEPROM_WREN)
144/* Input: <dev_addr> I2C address of EEPROM device to enable.
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100145 * <state> -1: deliver current state
146 * 0: disable write
Stefan Roese7644f162005-09-22 09:16:57 +0200147 * 1: enable write
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100148 * Returns: -1: wrong device address
149 * 0: dis-/en- able done
Stefan Roese7644f162005-09-22 09:16:57 +0200150 * 0/1: current state if <state> was -1.
151 */
152int eeprom_write_enable (unsigned dev_addr, int state) {
153 if (CFG_I2C_EEPROM_ADDR != dev_addr) {
154 return -1;
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100155 } else {
Stefan Roese7644f162005-09-22 09:16:57 +0200156 switch (state) {
157 case 1:
158 /* Enable write access, clear bit GPIO_SINT2. */
159 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
160 state = 0;
161 break;
162 case 0:
163 /* Disable write access, set bit GPIO_SINT2. */
164 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
165 state = 0;
166 break;
167 default:
168 /* Read current status back. */
169 state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
170 break;
171 }
172 }
173 return state;
174}
175#endif
176
177#if defined(CFG_EEPROM_WREN)
178int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
179{
180 int query = argc == 1;
181 int state = 0;
182
183 if (query) {
184 /* Query write access state. */
185 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
186 if (state < 0) {
187 puts ("Query of write access state failed.\n");
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100188 } else {
Stefan Roese7644f162005-09-22 09:16:57 +0200189 printf ("Write access for device 0x%0x is %sabled.\n",
190 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
191 state = 0;
192 }
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100193 } else {
Stefan Roese7644f162005-09-22 09:16:57 +0200194 if ('0' == argv[1][0]) {
195 /* Disable write access. */
196 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100197 } else {
Stefan Roese7644f162005-09-22 09:16:57 +0200198 /* Enable write access. */
199 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
200 }
201 if (state < 0) {
202 puts ("Setup of write access state failed.\n");
203 }
204 }
205
206 return state;
207}
208
209U_BOOT_CMD(
210 eepwren, 2, 0, do_eep_wren,
211 "eepwren - Enable / disable / query EEPROM write access\n",
212 NULL
213 );
214#endif /* #if defined(CFG_EEPROM_WREN) */