arch/mips/dts/brcm,bcm63268.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
 */

#include <dt-bindings/clock/bcm63268-clock.h>
#include <dt-bindings/dma/bcm63268-dma.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power-domain/bcm63268-power-domain.h>
#include <dt-bindings/reset/bcm63268-reset.h>
#include "skeleton.dtsi"

/ {
	compatible = "brcm,bcm63268";

	aliases {
		spi0 = &lsspi;
		spi1 = &hsspi;
	};

	cpus {
		reg = <0x10000000 0x4>;
		#address-cells = <1>;
		#size-cells = <0>;
		bootph-all;

		cpu@0 {
			compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
			device_type = "cpu";
			reg = <0>;
			bootph-all;
		};

		cpu@1 {
			compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
			device_type = "cpu";
			reg = <1>;
			bootph-all;
		};
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		bootph-all;

		hsspi_pll: hsspi-pll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <400000000>;
		};

		periph_osc: periph-osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <50000000>;
			bootph-all;
		};

		periph_clk: periph-clk {
			compatible = "brcm,bcm6345-clk";
			reg = <0x10000004 0x4>;
			#clock-cells = <1>;
		};

		timer_clk: timer-clk {
			compatible = "brcm,bcm6345-clk";
			reg = <0x100000ac 0x4>;
			#clock-cells = <1>;
		};
	};

	ubus {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		bootph-all;

		pll_cntl: syscon@10000008 {
			compatible = "syscon";
			reg = <0x10000008 0x4>;
		};

		syscon-reboot {
			compatible = "syscon-reboot";
			regmap = <&pll_cntl>;
			offset = <0x0>;
			mask = <0x1>;
		};

		periph_rst: reset-controller@10000010 {
			compatible = "brcm,bcm6345-reset";
			reg = <0x10000010 0x4>;
			#reset-cells = <1>;
		};

		wdt: watchdog@1000009c {
			compatible = "brcm,bcm6345-wdt";
			reg = <0x1000009c 0xc>;
			clocks = <&periph_osc>;
		};

		wdt-reboot {
			compatible = "wdt-reboot";
			wdt = <&wdt>;
		};

		gpio1: gpio-controller@100000c0 {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <20>;

			status = "disabled";
		};

		gpio0: gpio-controller@100000c4 {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x100000c4 0x4>, <0x100000cc 0x4>;
			gpio-controller;
			#gpio-cells = <2>;

			status = "disabled";
		};

		uart0: serial@10000180 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x10000180 0x18>;
			clocks = <&periph_osc>;

			status = "disabled";
		};

		uart1: serial@100001a0 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x100001a0 0x18>;
			clocks = <&periph_osc>;

			status = "disabled";
		};

		nand: nand-controller@10000200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,nand-bcm6368",
				     "brcm,brcmnand-v4.0",
				     "brcm,brcmnand";
			reg-names = "nand",
				    "nand-cache",
				    "nand-int-base";
			reg = <0x10000200 0x180>,
			      <0x10000600 0x200>,
			      <0x100000b0 0x10>;
			clocks = <&periph_clk BCM63268_CLK_NAND>;
			clock-names = "nand";

			status = "disabled";
		};

		periph_pwr: power-controller@1000184c {
			compatible = "brcm,bcm6328-power-domain";
			reg = <0x1000184c 0x4>;
			#power-domain-cells = <1>;
		};

		lsspi: spi@10000800 {
			compatible = "brcm,bcm6358-spi";
			reg = <0x10000800 0x70c>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&periph_clk BCM63268_CLK_SPI>;
			resets = <&periph_rst BCM63268_RST_SPI>;
			spi-max-frequency = <20000000>;
			num-cs = <8>;

			status = "disabled";
		};

		hsspi: spi@10001000 {
			compatible = "brcm,bcm6328-hsspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x10001000 0x600>;
			clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>;
			clock-names = "hsspi", "pll";
			resets = <&periph_rst BCM63268_RST_SPI>;
			spi-max-frequency = <50000000>;
			num-cs = <8>;

			status = "disabled";
		};

		leds: led-controller@10001900 {
			compatible = "brcm,bcm6328-leds";
			reg = <0x10001900 0x24>;
			#address-cells = <1>;
			#size-cells = <0>;

			status = "disabled";
		};

		ehci: usb-controller@10002500 {
			compatible = "brcm,bcm63268-ehci", "generic-ehci";
			reg = <0x10002500 0x100>;
			phys = <&usbh>;
			big-endian;

			status = "disabled";
		};

		ohci: usb-controller@10002600 {
			compatible = "brcm,bcm63268-ohci", "generic-ohci";
			reg = <0x10002600 0x100>;
			phys = <&usbh>;
			big-endian;

			status = "disabled";
		};

		usbh: usb-phy@10002700 {
			compatible = "brcm,bcm63268-usbh";
			reg = <0x10002700 0x38>;
			#phy-cells = <0>;
			clocks = <&periph_clk BCM63268_CLK_USBH>, <&timer_clk BCM63268_TCLK_USB_REF>;
			clock-names = "usbh", "usb_ref";
			power-domains = <&periph_pwr BCM63268_PWR_USBH>;
			resets = <&periph_rst BCM63268_RST_USBH>;

			status = "disabled";
		};

		memory-controller@10003000 {
			compatible = "brcm,bcm6328-mc";
			reg = <0x10003000 0x894>;
			bootph-all;
		};

		iudma: dma-controller@1000d800 {
			compatible = "brcm,bcm6368-iudma";
			reg = <0x1000d800 0x80>,
			      <0x1000da00 0x80>,
			      <0x1000dc00 0x80>;
			reg-names = "dma",
				    "dma-channels",
				    "dma-sram";
			#dma-cells = <1>;
			dma-channels = <8>;
		};

		enet: ethernet@10700000 {
			compatible = "brcm,bcm6368-enet";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x10700000 0x10000>;
			clocks = <&periph_clk BCM63268_CLK_GMAC>,
				 <&periph_clk BCM63268_CLK_ROBOSW>,
				 <&periph_clk BCM63268_CLK_ROBOSW250>,
				 <&timer_clk BCM63268_TCLK_EPHY1>,
				 <&timer_clk BCM63268_TCLK_EPHY2>,
				 <&timer_clk BCM63268_TCLK_EPHY3>,
				 <&timer_clk BCM63268_TCLK_GPHY>;
			resets = <&periph_rst BCM63268_RST_ENETSW>,
				 <&periph_rst BCM63268_RST_EPHY>,
				 <&periph_rst BCM63268_RST_GPHY>;
			dmas = <&iudma BCM63268_DMA_ENETSW_RX>,
			       <&iudma BCM63268_DMA_ENETSW_TX>;
			dma-names = "rx",
				    "tx";
			brcm,rgmii-override;
			brcm,rgmii-timing;

			status = "disabled";
		};
	};
};